SN74ALS166N屬于集成電路（IC）的移位寄存器。由美國德州儀器公司制造生產(chǎn)的SN74ALS166N移位寄存器移位寄存器是低級邏輯器件，通常用于在串行和并行方式之間轉(zhuǎn)換數(shù)字邏輯信號形式的數(shù)據(jù)，或在數(shù)字字內(nèi)移動數(shù)據(jù)位的位置。移位寄存器通常使用集成到一個設(shè)備中的一組觸發(fā)器來實現(xiàn)，常用于集成度更高的邏輯器件，但仍可用于 I/O 擴(kuò)展等應(yīng)用，在這些應(yīng)用中離散形式的函數(shù)可能會非常有用。

Synchronous Load

Direct Overriding Clear

Parallel-to-Serial Conversion

Package Options Include Plastic

Small-Outline (D) and Shrink Small-Outline

(DB) Packages and Standard Plastic (N) DIP

description

The SN74ALS166 parallel-load 8-bit shift register

is compatible with most other TTL logic families.

All inputs are buffered to lower the drive

requirements. Input clamping diodes minimize

switching transients and simplify system design.

These parallel-in or serial-in, serial-out registers have a complexity of 77 equivalent gates on the chip. They

feature gated clocks (CLK and CLK INH) inputs and an overriding clear (CLR) input. The parallel-in or serial-in

modes are established by the shift/load (SH/LD) input. When high, SH/LD enables the serial data (SER) input

and couples the eight flip-flops for serial shifting with each clock pulse. When low, the parallel (broadside) data

(A–H) inputs are enabled and synchronous loading occurs on the next clock pulse. During parallel loading, serial

data flow is inhibited. Clocking is accomplished on the low-to-high-level edge of the clock pulse through a

two-input positive-NOR gate, permitting one input to be used as a clock-enable or clock-inhibit function. Holding

either of the clock inputs high inhibits clocking; holding either low enables the other clock input. This allows the

system clock to be free running and the register can be stopped on command with the clock input. CLK INH

should be changed to the high level only when CLK is high. The buffered CLR overrides all other inputs, including

CLK, and sets all flip-flops to zero.

The SN74ALS166 is characterized for operation from 0°C to 70°C.