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SN74ACT7813-15DL.A中文資料德州儀器數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)

SN74ACT7813-15DL.A
廠商型號(hào)

SN74ACT7813-15DL.A

功能描述

64 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY

絲印標(biāo)識(shí)

ACT7813-15

封裝外殼

SSOP

文件大小

326.06 Kbytes

頁(yè)面數(shù)量

17 頁(yè)

生產(chǎn)廠商

TI2

中文名稱(chēng)

德州儀器

網(wǎng)址

網(wǎng)址

數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2025-8-16 20:00:00

人工找貨

SN74ACT7813-15DL.A價(jià)格和庫(kù)存,歡迎聯(lián)系客服免費(fèi)人工找貨

SN74ACT7813-15DL.A規(guī)格書(shū)詳情

Member of the Texas Instruments

WidebusE Family

Free-Running Read and Write Clocks Can

Be Asynchronous or Coincident

Read and Write Operations Synchronized

to Independent System Clocks

Input-Ready Flag Synchronized to Write

Clock

Output-Ready Flag Synchronized to Read

Clock

64 Words by 18 Bits

Low-Power Advanced CMOS Technology

Half-Full Flag and Programmable

Almost-Full/Almost-Empty Flag

Bidirectional Configuration and Width

Expansion Without Additional Logic

Fast Access Times of 12 ns With a 50-pF

Load and All Data Outputs Switching

Simultaneously

Data Rates up to 67 MHz

Pin-to-Pin Compatible With SN74ACT7803

and SN74ACT7805

Packaged in Shrink Small-Outline 300-mil

Package Using 25-mil Center-to-Center

Spacing

description

The SN74ACT7813 is a 64-word × 18-bit FIFO

suited for buffering asynchronous datapaths up to

67-MHz clock rates and 12-ns access times. Two

devices can be configured for bidirectional data buffering without additional logic. Multiple distributed VCC and

GND pins, along with Texas Instruments patented output edge control (OECE) circuit, dampen simultaneous

switching noise.

The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident.

Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2 is low, and input

ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN, OE1, and OE2 are low

and output ready (OR) is high. The first word written to memory is clocked through to the output buffer regardless

of the RDEN, OE1, and OE2 levels. The OR flag indicates that valid data is present on the output buffer.

The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET must be asserted while at least four

WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes

the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be

reset upon power up.

The SN74ACT7813 is characterized for operation from 0°C to 70°C.

供應(yīng)商 型號(hào) 品牌 批號(hào) 封裝 庫(kù)存 備注 價(jià)格
TI/德州儀器
24+
NA/
3274
原廠直銷(xiāo),現(xiàn)貨供應(yīng),賬期支持!
詢(xún)價(jià)
TI
23+
原廠封裝
28224
公司原裝現(xiàn)貨!主營(yíng)品牌!可含稅歡迎查詢(xún)
詢(xún)價(jià)
TI
22+
56-SSOP
5000
全新原裝,力挺實(shí)單
詢(xún)價(jià)
TI
2025+
SSOP-56
16000
原裝優(yōu)勢(shì)絕對(duì)有貨
詢(xún)價(jià)
TI
24+
5000
自己現(xiàn)貨
詢(xún)價(jià)
TI
22+
56SSOP
9000
原廠渠道,現(xiàn)貨配單
詢(xún)價(jià)
TI/德州儀器
25+
SSOP-56
860000
明嘉萊只做原裝正品現(xiàn)貨
詢(xún)價(jià)
TI/德州儀器
24+
SSOP-56
9600
原裝現(xiàn)貨,優(yōu)勢(shì)供應(yīng),支持實(shí)單!
詢(xún)價(jià)
TexasInstruments
18+
ICCLOCKEDFIFOMEMORY56-SS
6800
公司原裝現(xiàn)貨/歡迎來(lái)電咨詢(xún)!
詢(xún)價(jià)
羅徹斯特
22+
NA
500000
萬(wàn)三科技,秉承原裝,購(gòu)芯無(wú)憂(yōu)
詢(xún)價(jià)