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SN74ACT7803-15DL.A中文資料德州儀器數(shù)據(jù)手冊PDF規(guī)格書

SN74ACT7803-15DL.A
廠商型號

SN74ACT7803-15DL.A

功能描述

512 × 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY

絲印標識

ACT7803-15

封裝外殼

SSOP

文件大小

327.02 Kbytes

頁面數(shù)量

17

生產(chǎn)廠商 Texas Instruments
企業(yè)簡稱

TI2德州儀器

中文名稱

美國德州儀器公司官網(wǎng)

原廠標識
數(shù)據(jù)手冊

下載地址一下載地址二到原廠下載

更新時間

2025-8-1 17:45:00

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SN74ACT7803-15DL.A規(guī)格書詳情

Member of the Texas Instruments

WidebusE Family

Free-Running Read and Write Clocks Can

Be Asynchronous or Coincident

Read and Write Operations Synchronized

to Independent System Clocks

Input-Ready Flag Synchronized to Write

Clock

Output-Ready Flag Synchronized to Read

Clock

512 Words by 18 Bits

Low-Power Advanced CMOS Technology

Half-Full Flag and Programmable

Almost-Full/Almost-Empty Flag

Bidirectional Configuration and Width

Expansion Without Additional Logic

Fast Access Times of 12 ns With a 50-pF

Load and All Data Outputs Switching

Simultaneously

Data Rates up to 67 MHz

Pin-to-Pin Compatible With SN74ACT7805

and SN74ACT7813

Packaged in Shrink Small-Outline 300-mil

Package Using 25-mil Center-to-Center

Spacing

description

The SN74ACT7803 is a 512-word × 18-bit FIFO

suited for buffering asynchronous datapaths up to

67-MHz clock rates and 12-ns access times. Two devices can be configured for bidirectional data buffering

without additional logic. Multiple distributed VCC and GND pins, along with Texas Instruments patented output

edge control (OECE) circuit, dampen simultaneous switching noise.

The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident.

Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2 is low, and input

ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN, OE1, and OE2 are low

and output ready (OR) is high. The first word written to memory is clocked through to the output buffer,

regardless of the RDEN, OE1, and OE2 levels. The OR flag indicates that valid data is present on the output

buffer.

The FIFO can be reset asynchronously to WRTCLK and RDCLK. RESET must be asserted while at least four

WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO initializes

the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO must be

reset upon power up.

The SN74ACT7803 is characterized for operation from 0°C to 70°C.

供應商 型號 品牌 批號 封裝 庫存 備注 價格
TI
23+
原廠封裝
28057
公司原裝現(xiàn)貨!主營品牌!可含稅歡迎查詢
詢價
TI
24+
SSOP56
574
只做原裝,歡迎詢價,量大價優(yōu)
詢價
TI/德州儀器
22+
SSOP-48
3000
原裝正品,支持實單
詢價
TI
25+
SSOP56
4500
全新原裝、誠信經(jīng)營、公司現(xiàn)貨銷售!
詢價
TI
97+
SSOP/48
611
原裝現(xiàn)貨海量庫存歡迎咨詢
詢價
TI
22+
56-SSOP
5000
全新原裝,力挺實單
詢價
TI
2025+
SSOP-56
16000
原裝優(yōu)勢絕對有貨
詢價
TI
24+
5000
自己現(xiàn)貨
詢價
TI/德州儀器
24+
SSOP-56
9600
原裝現(xiàn)貨,優(yōu)勢供應,支持實單!
詢價
TexasInstruments
18+
ICCLOCKEDFIFOMEMORY56-SS
6800
公司原裝現(xiàn)貨/歡迎來電咨詢!
詢價