SN74ACT2226DWR屬于集成電路（IC）的FIFO存儲(chǔ)器。由美國(guó)德州儀器公司制造生產(chǎn)的SN74ACT2226DWRFIFO 存儲(chǔ)器先入先出 (FIFO) 存儲(chǔ)器可用于數(shù)字信息的短期存儲(chǔ)，其中信息檢索順序和序列與信息存儲(chǔ)順序和序列相同。這類(lèi)產(chǎn)品又稱(chēng)為隊(duì)列或緩沖存儲(chǔ)器，通常用于在單獨(dú)的設(shè)備之間交換信息，尤其是在數(shù)據(jù)以不同的速率或在略微不同的時(shí)間點(diǎn)生成和使用的情況下。

Dual Independent FIFOs Organized as:

64 Words by 1 Bit Each – SN74ACT2226

256 Words by 1 Bit Each – SN74ACT2228

Free-Running Read and Write Clocks Can

Be Asynchronous or Coincident on Each

FIFO

Input-Ready Flags Synchronized to Write

Clocks

Output-Ready Flags Synchronized to Read

Clocks

Half-Full and Almost-Full/Almost-Empty

Flags

Support Clock Frequencies up to 22 MHz

Access Times of 20 ns

Low-Power Advanced CMOS Technology

Packaged in 24-Pin Small-Outline

Integrated-Circuit Package

description

The SN74ACT2226 and SN74ACT2228 are dual FIFOs suited for a wide range of serial-data buffering

applications, including elastic stores for frequencies up to T2 telecommunication rates. Each FIFO on the chip

is arranged as 64 × 1 (SN74ACT2226) or 256 × 1 (SN74ACT2228) and has control signals and status flags for

independent operation. Output flags for each FIFO include input ready (1IR or 2IR), output ready (1OR or 2OR),

half full (1HF or 2HF), and almost full/almost empty (1AF/AE or 2AF/AE).

Serial data is written into a FIFO on the low-to-high transition of the write-clock (1WRTCLK or 2WRTCLK) input

when the write-enable (1WRTEN or 2WRTEN) input and input-ready flag (1IR or 2IR) output are both high.

Serial data is read from a FIFO on the low-to-high transition of the read-clock (1RDCLK or 2RDCLK) input when

the read-enable (1RDEN or 2RDEN) input and output-ready flag (1OR or 2OR) output are both high. The read

and write clocks of a FIFO can be asynchronous to one another.

Each input-ready flag (1IR or 2IR) is synchronized by two flip-flop stages to its write clock (1WRTCLK or

2WRTCLK), and each output-ready flag (1OR or 2OR) is synchronized by three flip-flop stages to its read clock

(1RDCLK or 2RDCLK). This multistage synchronization ensures reliable flag-output states when data is written

and read asynchronously.

A half-full flag (1HF or 2HF) is high when the number of bits stored in its FIFO is greater than or equal to half

the depth of the FIFO. An almost-full/almost-empty flag (1AF/AE or 2AF/AE) is high when eight or fewer bits

are stored in its FIFO and when eight or fewer empty locations are left in the FIFO. A bit present on the data

output is not stored in the FIFO.

The SN74ACT2226 and SN74ACT2228 are characterized for operation from –40°C to 85°C.

For more information on this device family, see the application report FIFOs With a Word Width of One Bit

(literature number SCAA006).