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SN74ACT2226DW.A中文資料德州儀器數(shù)據(jù)手冊(cè)PDF規(guī)格書

SN74ACT2226DW.A
廠商型號(hào)

SN74ACT2226DW.A

功能描述

DUAL 64 × 1, DUAL 256 × 1 CLOCKED FIRST-IN, FIRST-OUT MEMORIES

文件大小

593.52 Kbytes

頁(yè)面數(shù)量

23 頁(yè)

生產(chǎn)廠商

TI2

中文名稱

德州儀器

網(wǎng)址

網(wǎng)址

數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2025-8-10 23:01:00

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SN74ACT2226DW.A規(guī)格書詳情

Dual Independent FIFOs Organized as:

64 Words by 1 Bit Each – SN74ACT2226

256 Words by 1 Bit Each – SN74ACT2228

Free-Running Read and Write Clocks Can

Be Asynchronous or Coincident on Each

FIFO

Input-Ready Flags Synchronized to Write

Clocks

Output-Ready Flags Synchronized to Read

Clocks

Half-Full and Almost-Full/Almost-Empty

Flags

Support Clock Frequencies up to 22 MHz

Access Times of 20 ns

Low-Power Advanced CMOS Technology

Packaged in 24-Pin Small-Outline

Integrated-Circuit Package

description

The SN74ACT2226 and SN74ACT2228 are dual FIFOs suited for a wide range of serial-data buffering

applications, including elastic stores for frequencies up to T2 telecommunication rates. Each FIFO on the chip

is arranged as 64 × 1 (SN74ACT2226) or 256 × 1 (SN74ACT2228) and has control signals and status flags for

independent operation. Output flags for each FIFO include input ready (1IR or 2IR), output ready (1OR or 2OR),

half full (1HF or 2HF), and almost full/almost empty (1AF/AE or 2AF/AE).

Serial data is written into a FIFO on the low-to-high transition of the write-clock (1WRTCLK or 2WRTCLK) input

when the write-enable (1WRTEN or 2WRTEN) input and input-ready flag (1IR or 2IR) output are both high.

Serial data is read from a FIFO on the low-to-high transition of the read-clock (1RDCLK or 2RDCLK) input when

the read-enable (1RDEN or 2RDEN) input and output-ready flag (1OR or 2OR) output are both high. The read

and write clocks of a FIFO can be asynchronous to one another.

Each input-ready flag (1IR or 2IR) is synchronized by two flip-flop stages to its write clock (1WRTCLK or

2WRTCLK), and each output-ready flag (1OR or 2OR) is synchronized by three flip-flop stages to its read clock

(1RDCLK or 2RDCLK). This multistage synchronization ensures reliable flag-output states when data is written

and read asynchronously.

A half-full flag (1HF or 2HF) is high when the number of bits stored in its FIFO is greater than or equal to half

the depth of the FIFO. An almost-full/almost-empty flag (1AF/AE or 2AF/AE) is high when eight or fewer bits

are stored in its FIFO and when eight or fewer empty locations are left in the FIFO. A bit present on the data

output is not stored in the FIFO.

The SN74ACT2226 and SN74ACT2228 are characterized for operation from –40°C to 85°C.

For more information on this device family, see the application report FIFOs With a Word Width of One Bit

(literature number SCAA006).

供應(yīng)商 型號(hào) 品牌 批號(hào) 封裝 庫(kù)存 備注 價(jià)格
TI/德州儀器
24+
NA/
5072
原廠直銷,現(xiàn)貨供應(yīng),賬期支持!
詢價(jià)
TI
1815+
SOP24-7.2MM
6528
只做原裝正品現(xiàn)貨!或訂貨,假一賠十!
詢價(jià)
TI(德州儀器)
2024+
SOIC-24
500000
誠(chéng)信服務(wù),絕對(duì)原裝原盤
詢價(jià)
TI
25+
SOIC24
4500
全新原裝、誠(chéng)信經(jīng)營(yíng)、公司現(xiàn)貨銷售!
詢價(jià)
TEXAS
0406-
30
公司優(yōu)勢(shì)庫(kù)存 熱賣中!
詢價(jià)
TI
2025+
SOIC-24
16000
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詢價(jià)
TI
23+
SOP24-7.2MM
3200
正規(guī)渠道,只有原裝!
詢價(jià)
TI
22+
24-SOIC
5000
全新原裝,力挺實(shí)單
詢價(jià)
TI
24+
SOIC24
1349
詢價(jià)
TI/德州儀器
24+
SOIC-28
9600
原裝現(xiàn)貨,優(yōu)勢(shì)供應(yīng),支持實(shí)單!
詢價(jià)