Members of the Texas Instruments

Widebus+E Family

State-of-the-Art EPIC-IIBE BiCMOS Design

Significantly Reduces Power Dissipation

Latch-Up Performance Exceeds 500 mA Per

JEDEC Standard JESD-17

Typical VOLP (Output Ground Bounce)

< 0.8 V at VCC = 5 V, TA = 25°C

High-Impedance State During Power Up

and Power Down

Released as DSCC SMD 5962-9557801NXD

Distributed VCC and GND Pin Configuration

Minimizes High-Speed Switching Noise

High-Drive Outputs (–32-mA IOH, 64-mA IOL)

Bus Hold on Data Inputs Eliminates the

Need for External Pullup/Pulldown

Resistors

Package Options Include 100-Pin Plastic

Thin Quad Flat (PZ) Package With

14 × 14-mm Body Using 0.5-mm Lead Pitch

and Space-Saving 100-Pin Ceramic Quad

Flat (HS) Package?