SN74ABT2952ADWR屬于集成電路（IC）的緩沖器驅(qū)動(dòng)器接收器收發(fā)器。由美國德州儀器公司制造生產(chǎn)的SN74ABT2952ADWR緩沖器，驅(qū)動(dòng)器，接收器，收發(fā)器邏輯緩沖器、驅(qū)動(dòng)器、接收器和收發(fā)器允許隔離對(duì)某個(gè)電路的邏輯信號(hào)的訪問，以用于另一電路。緩沖器將其輸入信號(hào)（不變或反相）傳遞到其輸出，并可能用于清除弱信號(hào)或驅(qū)動(dòng)負(fù)載。在布爾邏輯仿真器中，緩沖器主要用于增加傳播延遲。邏輯接收器和收發(fā)器允許在數(shù)據(jù)總線之間進(jìn)行隔離通信。

State-of-the-Art EPIC-IIBE BiCMOS Design

Significantly Reduces Power Dissipation

Two 8-Bit Back-to-Back Registers Store

Data Flowing in Both Directions

Noninverting Outputs

Typical VOLP (Output Ground Bounce) < 1 V

at VCC = 5 V, TA = 25°C

Latch-Up Performance Exceeds 500 mA Per

JESD 17

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

Package Options Include Plastic

Small-Outline (DW), Shrink Small-Outline

(DB), and Thin Shrink Small-Outline (PW)

Packages, Ceramic Chip Carriers (FK),

Ceramic Flat (W) Package, and Plastic (NT)

and Ceramic (JT) DIPs

description

The ’ABT2952A transceivers consist of two 8-bit

back-to-back registers that store data flowing in

both directions between two bidirectional buses.

Data on the A or B bus is stored in the registers on

the low-to-high transition of the clock (CLKAB or

CLKBA) input provided that the clock-enable

(CLKENAB or CLKENBA) input is low. Taking the

output-enable (OEAB or OEBA) input low

accesses the data on either port.

To ensure the high-impedance state during power

up or power down, OE should be tied to VCC

through a pullup resistor; the minimum value of

the resistor is determined by the current-sinking

capability of the driver.

The SN54ABT2952A is characterized for

operation over the full military temperature range

of –55°C to 125°C. The SN74ABT2952A is

characterized for operation from –40°C to 85°C.