SN74ABT16646DLR屬于集成電路（IC）的緩沖器驅(qū)動(dòng)器接收器收發(fā)器。由美國(guó)德州儀器公司制造生產(chǎn)的SN74ABT16646DLR緩沖器，驅(qū)動(dòng)器，接收器，收發(fā)器邏輯緩沖器、驅(qū)動(dòng)器、接收器和收發(fā)器允許隔離對(duì)某個(gè)電路的邏輯信號(hào)的訪問(wèn)，以用于另一電路。緩沖器將其輸入信號(hào)（不變或反相）傳遞到其輸出，并可能用于清除弱信號(hào)或驅(qū)動(dòng)負(fù)載。在布爾邏輯仿真器中，緩沖器主要用于增加傳播延遲。邏輯接收器和收發(fā)器允許在數(shù)據(jù)總線之間進(jìn)行隔離通信。

Members of the Texas Instruments

WidebusE Family

State-of-the-Art EPIC-IIBE BiCMOS Design

Significantly Reduces Power Dissipation

Latch-Up Performance Exceeds 500 mA Per

JESD 17

Typical VOLP (Output Ground Bounce) < 1 V

at VCC = 5 V, TA = 25°C

Distributed VCC and GND Pin Configuration

Minimizes High-Speed Switching Noise

Flow-Through Architecture Optimizes PCB

Layout

High-Drive Outputs (–32-mA IOH, 64-mA IOL)

Package Options Include Plastic Shrink

Small-Outline (DL), Thin Shrink

Small-Outline (DGG) Packages and 380-mil

Fine-Pitch Ceramic Flat (WD) Package

Using 25-mil Center-to-Center Spacings

description

The ’ABT16646 devices consist of

bus-transceiver circuits, D-type flip-flops, and

control circuitry arranged for multiplexed

transmission of data directly from the input bus or

from the internal registers.

These devices can be used as two 8-bit

transceivers or one 16-bit transceiver. Data on the

A or B bus is clocked into the registers on the

low-to-high transition of the appropriate clock

(CLKAB or CLKBA) input. Figure 1 illustrates the

four fundamental bus-management functions that

can be performed with the ’ABT16646 devices.

Output-enable (OE) and direction-control (DIR) inputs are provided to control the transceiver functions. In the

transceiver mode, data present at the high-impedance port may be stored in either register or in both. The

select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. The circuitry

used for select control eliminates the typical decoding glitch that occurs in a multiplexer during the transition

between stored and real-time data. The direction control (DIR) determines which bus receives data when OE

is low. In the isolation mode (OE high), A data can be stored in one register and/or B data can be stored in the

other register.

When an output function is disabled, the input function is still enabled and can be used to store and transmit

data. Only one of the two buses, A or B, can be driven at a time.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.