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SN65MLVD2

SINGLE M-LVDS RECEIVERS

FEATURES ·Low-VoltageDifferential30-Wto55-WLine ReceiversforSignalingRates(1)upto 250Mbps;ClockFrequenciesupto125MHz ·SN65MLVD2Type-1ReceiverIncorporates25 mVofInputThresholdHysteresis ·SN65MLVD3Type-2ReceiverProvides100 mVOffsetThresholdtoDetectOpen-Circu

SN65MLVD2

單通道 M-LVDS 1 類(lèi)接收器; ? Low-Voltage Differential 30- Line Receivers for Signaling Rates\n up to 250Mbps; Clock Frequencies up to 125MHz\n? SN65MLVD2 Type-1 Receiver Incorporates 25 mV of Input Threshold Hysteresis\n? SN65MLVD3 Type-2 Receiver Provides 100 mV Offset Threshold to Detect Open-Circuit and Idle-Bus Conditions\n? Wide Receiver Input Common-Mode Voltage Range, -1 V to 3.4 V, Allows 2 V of Ground Noise\n? Improved VIT (35 mV)\n? Meets or Exceeds the M-LVDS Standard TIA/EIA-899 for Multipoint Topology\n? High Input Impedance with Low Supply Voltage\n? Bus-Pin HBM ESD Protection Exceeds 9 kV\n? Packaged in 8-Pin SON (DRB) 70% Smaller Than 8-Pin SOIC\n? APPLICATIONS \n? Parallel Multipoint Data and Clock Transmission via Backplanes and Cables\n? Cellular Base Stations\n? Central Office Switches\n? Network Switches and Routers\n \n \n The signaling rate of a line is the number of voltage transitions that are made per second, expressed in the units bps (bits per second).;

The SN65MLVD2 and SN65MLVD3 are single-channel M-LVDS receivers. These devices are designed in full compliance with the TIA/EIA-899 (M-LVDS) standard, which are optimized to operate at signaling rates up to 250 Mbps. Each receiver channel is controlled by a receive enable (RE). When RE = low, the corresponding channel is enabled; when RE = high, the corresponding channel is disabled. The M-LVDS standard defines two types of receivers, designated as Type-1 and Type-2. Type-1 receivers (SN65MLVD2) have thresholds centered about zero with 25 mV of hysteresis to prevent output oscillations with loss of input; Type-2 receivers (SN65MLVD3) implement a failsafe by using an offset threshold. Receiver outputs are slew rate controlled to reduce EMI and crosstalk effects associated with large current surges. The devices are characterized for operation from -40°C to 85°C.

SN65MLVD2

SINGLE M-LVDS RECEIVERS

SN65MLVD200A

半雙工 M-LVDS 收發(fā)器; ? Low-Voltage Differential 30-Ω to 55-Ω Line Drivers and Receivers for Signaling Rates\n up to 100 Mbps, Clock Frequencies up to 50 MHz\n? Type-1 Receivers Incorporate 25 mV of Hysteresis (SN65MLVD200A, SN65MLVD202A)\n? Type-2 Receivers Provide an Offset (100 mV) Threshold to Detect Open-Circuit and Idle-Bus Conditions (SN65MLVD204A, SN65MLVD205A)\n? Meets or Exceeds the M-LVDS Standard TIA/EIA-899 for Multipoint Data Interchange\n? Controlled Driver Output Voltage Transition Times for Improved Signal Quality\n? –1 V to 3.4 V of Common-Mode Voltage Range Allows Data Transfer With 2 V of Ground Noise\n? Bus Pins High Impedance When Disabled or VCC ≤ 1.5 V\n? 200-Mbps Devices Available (SN65MLVD201, SN65MLVD203, SN65MLVD206, SN65MLVD207)\n? Bus Pin ESD Protection Exceeds 8 kV\n? Packages Available: \n - 8-Pin SOIC SN65MLVD200A, SN65MLVD204A\n? 14-Pin SOIC SN65MLVD202A, SN65MLVD205A\n? Improved Alternatives to the SN65MLVD200, SN65MLVD202A, SN65MLVD204A, and SN65MLVD205A Devices;

The SN65MLVD20xx devices are multipoint low-voltage differential (M-LVDS) line drivers and receivers that are optimized to operate at signaling rates up to 100 Mbps. All parts comply with the multipoint low-voltage differential signaling (M-LVDS) standard TIA/EIA-899.\nThe SN65MLVD20xx devices have enhancements over their predecessors. Improved features include controlled slew rate on the driver output to help minimize reflections from unterminated stubs, which results in better signal integrity. Additionally, 8-kV ESD protection on the bus pins for more robustness. The same footprint definition was maintained making for an easy drop-in replacement for a system performance upgrade.\nThe devices are characterized for operation from –40°C to 85°C.\n \n

SN65MLVD2DRBR

絲?。?a target="_blank" title="Marking" href="/mf2/marking.html">MF2；Package：SON；SINGLE M-LVDS RECEIVERS

FEATURES ·Low-VoltageDifferential30-Wto55-WLine ReceiversforSignalingRates(1)upto 250Mbps;ClockFrequenciesupto125MHz ·SN65MLVD2Type-1ReceiverIncorporates25 mVofInputThresholdHysteresis ·SN65MLVD3Type-2ReceiverProvides100 mVOffsetThresholdtoDetectOpen-Circu

SN65MLVD2DRBR.B

絲?。?a target="_blank" title="Marking" href="/mf2/marking.html">MF2；Package：SON；SINGLE M-LVDS RECEIVERS

FEATURES ·Low-VoltageDifferential30-Wto55-WLine ReceiversforSignalingRates(1)upto 250Mbps;ClockFrequenciesupto125MHz ·SN65MLVD2Type-1ReceiverIncorporates25 mVofInputThresholdHysteresis ·SN65MLVD3Type-2ReceiverProvides100 mVOffsetThresholdtoDetectOpen-Circu

SN65MLVD2DRBT

絲?。?a target="_blank" title="Marking" href="/mf2/marking.html">MF2；Package：SON；SINGLE M-LVDS RECEIVERS

FEATURES ·Low-VoltageDifferential30-Wto55-WLine ReceiversforSignalingRates(1)upto 250Mbps;ClockFrequenciesupto125MHz ·SN65MLVD2Type-1ReceiverIncorporates25 mVofInputThresholdHysteresis ·SN65MLVD3Type-2ReceiverProvides100 mVOffsetThresholdtoDetectOpen-Circu

SN65MLVD2DRBT.B

絲印：MF2；Package：SON；SINGLE M-LVDS RECEIVERS

FEATURES ·Low-VoltageDifferential30-Wto55-WLine ReceiversforSignalingRates(1)upto 250Mbps;ClockFrequenciesupto125MHz ·SN65MLVD2Type-1ReceiverIncorporates25 mVofInputThresholdHysteresis ·SN65MLVD3Type-2ReceiverProvides100 mVOffsetThresholdtoDetectOpen-Circu

SN65MLVD2DRBTG4.B

絲印：MF2；Package：SON；SINGLE M-LVDS RECEIVERS

FEATURES ·Low-VoltageDifferential30-Wto55-WLine ReceiversforSignalingRates(1)upto 250Mbps;ClockFrequenciesupto125MHz ·SN65MLVD2Type-1ReceiverIncorporates25 mVofInputThresholdHysteresis ·SN65MLVD3Type-2ReceiverProvides100 mVOffsetThresholdtoDetectOpen-Circu

SN65MLVD200

MULTIPOINT-LVDS LINE DRIVERS AND RECEIVERS