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SN65LVELT23

3.3V 雙路差動 LVPECL 緩沖器至 LVTTL 轉(zhuǎn)換器; ? Dual 3.3-VDifferential LVPECL/LVDS to LVTTL Buffer Translator\n? 24-mA LVTTL Ouputs\n? Operating Range \n - PECL VCC = 3 V to 3.6 V With GND = 0 V\n? Support for Clock Frequenciesto >180 MHz\n? 2-ns Typical Propagation Delay\n? Internal Input Pullup and Pulldown Resistors\n? Built-in Temperature Compensation\n? Drop-In Compatible to MC100LVELT23\n? APPLICATIONS \n - Data and Clock Transmission Over Backplane\n? Signaling Level Conversion for Clock or Data;

The SN65LVELT23 is a low-power dual LVPECL/LVDS to LVTTL translator device. The device includes circuitry to maintain inputs at VCC/2 when left open.The SN65LVELT23 is housed in an industry-standard SOIC-8 package and is also available in a TSSOP-8 option.\n \n

SN65LVELT23

3.3-V Dual Differential LVPECL/LVDS Buffer to LVTTL Translator

SN65LVELT23D

絲?。?a target="_blank" title="Marking" href="/lvel23/marking.html">LVEL23；Package：SOIC；3.3-V Dual Differential LVPECL/LVDS Buffer to LVTTL Translator

1FEATURES ·Dual3.3-VDifferentialLVPECL/LVDStoLVTTL BufferTranslator ·24-mALVTTLOuputs ·OperatingRange –PECLVCC=3Vto3.6VWith GND=0V ·SupportforClockFrequenciesto>180MHz ·2-nsTypicalPropagationDelay ·InternalInputPullupandPulldownResistors ·Built-i

SN65LVELT23D.B

絲?。?a target="_blank" title="Marking" href="/lvel23/marking.html">LVEL23；Package：SOIC；3.3-V Dual Differential LVPECL/LVDS Buffer to LVTTL Translator

1FEATURES ·Dual3.3-VDifferentialLVPECL/LVDStoLVTTL BufferTranslator ·24-mALVTTLOuputs ·OperatingRange –PECLVCC=3Vto3.6VWith GND=0V ·SupportforClockFrequenciesto>180MHz ·2-nsTypicalPropagationDelay ·InternalInputPullupandPulldownResistors ·Built-i

SN65LVELT23DGK

絲印：SIMI；Package：MSOP；3.3-V Dual Differential LVPECL/LVDS Buffer to LVTTL Translator

1FEATURES ·Dual3.3-VDifferentialLVPECL/LVDStoLVTTL BufferTranslator ·24-mALVTTLOuputs ·OperatingRange –PECLVCC=3Vto3.6VWith GND=0V ·SupportforClockFrequenciesto>180MHz ·2-nsTypicalPropagationDelay ·InternalInputPullupandPulldownResistors ·Built-i

SN65LVELT23DGK.B

絲?。?a target="_blank" title="Marking" href="/simi/marking.html">SIMI；Package：VSSOP；3.3-V Dual Differential LVPECL/LVDS Buffer to LVTTL Translator

1FEATURES ·Dual3.3-VDifferentialLVPECL/LVDStoLVTTL BufferTranslator ·24-mALVTTLOuputs ·OperatingRange –PECLVCC=3Vto3.6VWith GND=0V ·SupportforClockFrequenciesto>180MHz ·2-nsTypicalPropagationDelay ·InternalInputPullupandPulldownResistors ·Built-i

SN65LVELT23DGKR

絲?。?a target="_blank" title="Marking" href="/simi/marking.html">SIMI；Package：VSSOP；3.3-V Dual Differential LVPECL/LVDS Buffer to LVTTL Translator

1FEATURES ·Dual3.3-VDifferentialLVPECL/LVDStoLVTTL BufferTranslator ·24-mALVTTLOuputs ·OperatingRange –PECLVCC=3Vto3.6VWith GND=0V ·SupportforClockFrequenciesto>180MHz ·2-nsTypicalPropagationDelay ·InternalInputPullupandPulldownResistors ·Built-i

SN65LVELT23DGKR.B

絲?。?a target="_blank" title="Marking" href="/simi/marking.html">SIMI；Package：VSSOP；3.3-V Dual Differential LVPECL/LVDS Buffer to LVTTL Translator

1FEATURES ·Dual3.3-VDifferentialLVPECL/LVDStoLVTTL BufferTranslator ·24-mALVTTLOuputs ·OperatingRange –PECLVCC=3Vto3.6VWith GND=0V ·SupportforClockFrequenciesto>180MHz ·2-nsTypicalPropagationDelay ·InternalInputPullupandPulldownResistors ·Built-i

SN65LVELT23DR

絲?。?a target="_blank" title="Marking" href="/lvel23/marking.html">LVEL23；Package：SOIC；3.3-V Dual Differential LVPECL/LVDS Buffer to LVTTL Translator

1FEATURES ·Dual3.3-VDifferentialLVPECL/LVDStoLVTTL BufferTranslator ·24-mALVTTLOuputs ·OperatingRange –PECLVCC=3Vto3.6VWith GND=0V ·SupportforClockFrequenciesto>180MHz ·2-nsTypicalPropagationDelay ·InternalInputPullupandPulldownResistors ·Built-i

SN65LVELT23DR.B

絲印：LVEL23；Package：SOIC；3.3-V Dual Differential LVPECL/LVDS Buffer to LVTTL Translator

1FEATURES ·Dual3.3-VDifferentialLVPECL/LVDStoLVTTL BufferTranslator ·24-mALVTTLOuputs ·OperatingRange –PECLVCC=3Vto3.6VWith GND=0V ·SupportforClockFrequenciesto>180MHz ·2-nsTypicalPropagationDelay ·InternalInputPullupandPulldownResistors ·Built-i