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SN65LVDS94數(shù)據(jù)手冊集成電路(IC)的串行器解串器規(guī)格書PDF

| 廠商型號 |
SN65LVDS94 |
| 參數(shù)屬性 | SN65LVDS94 封裝/外殼為56-TFSOP(0.240",6.10mm 寬);包裝為卷帶(TR);類別為集成電路(IC)的串行器解串器;產(chǎn)品描述:IC LVDS SERDES RECEIVER 56-TSSOP |
| 功能描述 | Serdes 解串器 |
| 封裝外殼 | 56-TFSOP(0.240",6.10mm 寬) |
| 制造商 | TI Texas Instruments |
| 中文名稱 | 德州儀器 美國德州儀器公司 |
| 數(shù)據(jù)手冊 | |
| 更新時間 | 2025-8-20 8:39:00 |
| 人工找貨 | SN65LVDS94價格和庫存,歡迎聯(lián)系客服免費人工找貨 |
SN65LVDS94規(guī)格書詳情
描述 Description
The SN65LVDS94 LVDS serdes (serializer/deserializer) receiver contains four serial-in 7-bit parallel-out shift registers, a 7× clock synthesizer, and five low-voltage differential signaling (LVDS) line receivers in a single integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such as the SN65LVDS93 and SN65LVDS95, over five balanced-pair conductors and expansion to 28 bits of single-ended LVTTL synchronous data at a lower transfer rate. When receiving, the high-speed LVDS data is received and loaded into registers at the rate seven times the LVDS input clock (CLKIN). The data is then unloaded to a 28-bit wide LVTTL parallel bus at the CLKIN rate. A phase-locked loop clock synthesizer circuit generates a 7× clock for internal clocking and an output clock for the expanded data. The SN65LVDS94 presents valid data on the rising edge of the output clock (CLKOUT). The SN65LVDS94 requires only five line termination resistors for the differential inputs and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user intervention is the possible use of the shutdown/clear (SHTDN\\) active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low level on this signal clears all internal registers to a low level. The SN65LVDS94 is characterized for operation over ambient air temperatures of -40°C to 85°C.
特性 Features
? 4:28 Data Channel Expansion at up to 1.904 Gigabits per Second Throughput
? Suited for Point-to-Point Subsystem Communication With Very Low EMI
? 4 Data Channels and Clock Low-Voltage Differential Channels in and 28 Data and Clock Out Low-Voltage TTL Channels Out
? Operates From a Single 3.3-V Supply and 250 mW (Typ)
? 5-V Tolerant SHTDN\\ Input
? Rising Clock Edge Triggered Outputs
? Bus Pins Tolerate 4-kV HBM ESD
? Packaged in Thin Shrink Small-Outline Package With 20 Mil Terminal Pitch
? Consumes
? No External Components Required for PLL
? Meets or Exceeds the Requirements of ANSI EIA/TIA-644 Standard
? Industrial Temperature Qualified TA = -40°C to 85°C
? Replacement for the DS90CR286
技術(shù)參數(shù)
- 產(chǎn)品編號:
SN65LVDS94DGGG4
- 制造商:
Texas Instruments
- 類別:
集成電路(IC) > 串行器,解串器
- 包裝:
卷帶(TR)
- 功能:
解串器
- 數(shù)據(jù)速率:
1.904Gbps
- 輸入類型:
LVDS
- 輸出類型:
LVTTL
- 輸入數(shù):
4
- 輸出數(shù):
28
- 電壓 - 供電:
3V ~ 3.6V
- 工作溫度:
-40°C ~ 85°C(TA)
- 安裝類型:
表面貼裝型
- 封裝/外殼:
56-TFSOP(0.240",6.10mm 寬)
- 供應(yīng)商器件封裝:
56-TSSOP
- 描述:
IC LVDS SERDES RECEIVER 56-TSSOP
| 供應(yīng)商 | 型號 | 品牌 | 批號 | 封裝 | 庫存 | 備注 | 價格 |
|---|---|---|---|---|---|---|---|
TI(德州儀器) |
2021+ |
TSSOP-56 |
499 |
詢價 | |||
TI |
23+ |
TSSOP56 |
5000 |
全新原裝,支持實單,非誠勿擾 |
詢價 | ||
TI |
22+ |
56-TSSOP |
5000 |
全新原裝,力挺實單 |
詢價 | ||
TEXAS INSTRUMENTS |
2022+ |
原廠原包裝 |
8600 |
全新原裝 支持表配單 中國著名電子元器件獨立分銷 |
詢價 | ||
TI |
23+ |
NA |
20000 |
詢價 | |||
TI(德州儀器) |
24+ |
NA/ |
7350 |
現(xiàn)貨供應(yīng),當(dāng)天可交貨!免費送樣,原廠技術(shù)支持!!! |
詢價 | ||
TI |
23+ |
TSSOP |
8650 |
受權(quán)代理!全新原裝現(xiàn)貨特價熱賣! |
詢價 | ||
TI |
24+ |
09+ |
5 |
原裝現(xiàn)貨假一罰十 |
詢價 | ||
TI(德州儀器) |
24+ |
NA/ |
8735 |
原廠直銷,現(xiàn)貨供應(yīng),賬期支持! |
詢價 | ||
TI |
23+ |
NA |
20000 |
全新原裝假一賠十 |
詢價 |

