SN65LVDS93DGGR屬于集成電路（IC）的串行器解串器。由美國(guó)德州儀器公司制造生產(chǎn)的SN65LVDS93DGGR串行器，解串器串行器將并行提供的信息轉(zhuǎn)換為較高符號(hào)率的串行數(shù)據(jù)流，從而減少數(shù)字信息傳輸所需的導(dǎo)線數(shù)量；解串器執(zhí)行相反的功能。常用于在圖像傳感器、圖像處理器和顯示器之間傳輸視頻數(shù)據(jù)，還有針對(duì)工業(yè) I/O 設(shè)備等其他應(yīng)用而定制的器件。

1FEATURES

· 28:4 Data Channel Compression at up to

1.904 Gigabits per Second Throughput

· Suited for Point-to-Point Subsystem

Communication With Very Low EMI

· 28 Data Channels Plus Clock in Low-Voltage

TTL and 4 Data Channels Plus Clock Out

Low-Voltage Differential

· Selectable Rising or Falling Clock Edge

Triggered Inputs

· Bus Pins Tolerate 6-kV HBM ESD

· Operates From a Single 3.3-V Supply and

250 mW (Typ)

· 5-V Tolerant Data Inputs

· Packaged in Thin Shrink Small-Outline

Package With 20 Mil Terminal Pitch

· Consumes <1 mW When Disabled

· Wide Phase-Lock Input Frequency Range

20 MHz to 68 MHz

· No External Components Required for PLL

· Outputs Meet or Exceed the Requirements of

ANSI EIA/TIA-644 Standard

· Industrial Temperature Qualified TA = –40°C

to 85°C

· Replacement for the DS90CR285

DESCRIPTION

The SN65LVDS93 LVDS serdes (serializer/

deserializer) transmitter contains four 7-bit parallelload

serial-out shift registers, a 7 ?clock synthesizer,

and five low-voltage differential signaling (LVDS)

drivers in a single integrated circuit. These functions

allow 28 bits of single-ended LVTTL data to be

synchronously transmitted over five balanced-pair

conductors for receipt by a compatible receiver, such

as the SN65LVDS94.

When transmitting, data bits D0 through D27 are

each loaded into registers upon the edge of the input

clock signal (CLKIN). The rising or falling edge of the clock can be selected via the clock select (CLKSEL)

pin. The frequency of CLKIN is multiplied seven times

and then used to serially unload the data registers in

7-bit slices. The four serial streams and a

phase-locked clock (CLKOUT) are then output to

LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.