SN65LVDS17DRFT屬于集成電路（IC）的信號緩沖器、中繼器、分離器。由美國德州儀器公司制造生產(chǎn)的SN65LVDS17DRFT信號緩沖器、中繼器、分離器信號緩沖器、中繼器和分離器系列中的產(chǎn)品適用于遠距離電氣互連或電纜系統(tǒng)的數(shù)字信息傳輸。所有實際互連系統(tǒng)都具有非理想特性，該系列產(chǎn)品主要用于解決數(shù)字信息傳輸過程中因此造成的模擬問題。此外，還有其他功能，例如不同物理接口樣式之間的轉換和多路復用。

FEATURES

· Low-Voltage PECL Input and Low-Voltage

PECL or LVDS Outputs

· Clock Rates to 2 GHz

– 140-ps Output Transition Times

– 0.11 ps Typical Intrinsic Phase Jitter

– Less than 630 ps Propagation Delay Times

· 2.5-V or 3.3-V Supply Operation

· 2-mm × 2-mm Small-Outline

No-Lead Package

APPLICATIONS

· PECL-to-LVDS Translation

· Clock Signal Amplification

DESCRIPTION

These four devices are high-frequency oscillator gain stages supporting both LVPECL or LVDS on the high gain

outputs in 3.3-V or 2.5-V systems. Additionally, provides the option of both single-ended input (PECL levels on

the SN65LVx16) and fully differential inputs on the SN65LVx17.

The SN65LVx16 provides the user a Gain Control (GC) for controlling the Q output from 300 mV to 860 mV

either by leaving it open (NC), grounded, or tied to VCC. (When left open, the Q output defaults to 575 mV.) The

Q on the SN65LVx17 defaults to 575 mV as well.

Both devices provide a voltage reference (VBB) of typically 1.35 V below VCC for use in receiving single-ended

PECL input signals. When not used, VBB should be unconnected or open.

All devices are characterized for operation from –40°C to 85°C.