SN65LVDS150PWG4屬于集成電路（IC）的時鐘發(fā)生器PLL頻率合成器。由美國德州儀器公司制造生產(chǎn)的SN65LVDS150PWG4時鐘發(fā)生器，PLL，頻率合成器時鐘發(fā)生器、PLL 和頻率合成器集成電路 (IC) 可為邏輯器件提供參考信號的穩(wěn)定定時脈沖，這些器件包括計算機(jī)、微控制器、數(shù)據(jù)通信系統(tǒng)和圖形/視頻發(fā)生器。這些集成電路可能包括緩沖器、驅(qū)動器、分頻器、倍頻器、多路復(fù)用器、合成器、扇出分配器和預(yù)分頻器。

FEATURES

· A Member of the MuxIt? Serializer-

Deserializer Building-Block Chip Family

· Pin Selectable Frequency Multiplier Ratios

Between 4 and 40

· Input Clock Frequencies From 5 to 50 MHz

· Multiplied Clock Frequencies up to

400 MHz

· Internal Loop Filters and Low PLL-Jitter of

20 ps RMS Typical at 200 MHz

· LVDS Compatible Differential Inputs and

Outputs Meet or Exceed the Requirements of

ANSI EIA/TIA-644-A

· LVTTL Compatible Inputs Are 5 V Tolerant

· LVDS Inputs and Outputs ESD Protection

Exceeds 12 kV HBM

· Operates From a Single 3.3 V Supply

· Packaged in 28-Pin Thin Shrink Small-Outline

Package With 26 mil Terminal Pitch

DESCRIPTION

The MuxIt is a family of general-purpose, multiple-chip building blocks for implementing parallel data serializers

and deserializers. The system allows for wide parallel data to be transmitted through a reduced number of

differential transmission lines over distances greater than can be achieved with a single-ended (e.g., LVTTL or

LVCMOS) data interface. The number of bits multiplexed per transmission line is user selectable, allowing for

higher transmission efficiencies than with other existing fixed ratio solutions. Muxlt utilizes the LVDS

(TIA/EIA-644) low voltage differential signaling technology for communications between the data source and data

destination.

The MuxIt family initially includes three devices supporting simplex communications; The SN65LVDS150 Phase

Locked Loop-Frequency Multiplier, The SN65LVDS151 Serializer-Transmitter, and The SN65LVDS152

Receiver-Deserializer.

The SN65LVDS150 is a PLL based frequency multiplier designed for use with the other members of the MuxIt

family of serializers and deserializers. The frequency multiplication ratio is pin selectable over a wide range of

values from 4 through 40 to accommodate a broad spectrum of user needs. No external filter components are

needed. A PLL lock indicator output is available which may be used to enable link data transfers.

The design of the SN65LVDS150 allows it to be used at either the transmit end or the receive end of the MuxIt

serial link. The differential clock reference input (CRI) is driven by the system's parallel data clock when at the

source end of the link, or by the link clock when at the destination end of the link. The differential clock reference

input may be driven by either an LVDS differential signal, or by a single ended clock of either polarity. For

single-ended use the nonclocked input is biased to the logic threshold voltage. A VCC/2 threshold reference, VT,

is provided on a pin adjacent the differential CRI pins for convenience when the input is used in a single-ended

mode.