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首頁>SN65LBC176AMDREP.A>規(guī)格書詳情

SN65LBC176AMDREP.A中文資料德州儀器數(shù)據(jù)手冊PDF規(guī)格書

SN65LBC176AMDREP.A
廠商型號

SN65LBC176AMDREP.A

功能描述

DIFFERENTIAL BUS TRANSCEIVER

絲印標(biāo)識

176MEP

封裝外殼

SOIC

文件大小

525.57 Kbytes

頁面數(shù)量

21

生產(chǎn)廠商 Texas Instruments
企業(yè)簡稱

TI2德州儀器

中文名稱

美國德州儀器公司官網(wǎng)

原廠標(biāo)識
數(shù)據(jù)手冊

下載地址一下載地址二到原廠下載

更新時間

2025-8-4 23:00:00

人工找貨

SN65LBC176AMDREP.A價格和庫存,歡迎聯(lián)系客服免費(fèi)人工找貨

SN65LBC176AMDREP.A規(guī)格書詳情

Controlled Baseline

? One Assembly/Test Site, One Fabrication

Site

Extended Temperature Performance of

?40°C to 125°C and ?55°C to 125°C

Enhanced Diminishing Manufacturing

Sources (DMS) Support

Enhanced Product Change Notification

Qualification Pedigree?

High-Speed Low-Power LinBiCMOS?

Circuitry Designed for Signaling Rates? Up

to 30 Mbps

Bus-Pin ESD Protection Exceeds 12-kV

HBM

Compatible With ANSI Standard

TIA/EIA-485-A and ISO 8482:1987(E)

Low Skew

Designed for Multipoint Transmission on

Long Bus Lines in Noisy Environments

Low Disabled Supply Current

Requirements . . . 700 μA Maximum

Common-Mode Voltage Range of ?7 V

to 12 V

Thermal-Shutdown Protection

Driver Positive and Negative Current

Limiting

Open-Circuit Fail-Safe Receiver Design

Receiver Input Sensitivity . . . ±200 mV Max

Receiver Input Hysteresis . . . 50 mV Typ

Glitch-Free Power-Up and Power-Down

Protection

description/ordering information

The SN65LBC176A-EP differential bus transceiver is a monolithic, integrated circuits designed for bidirectional

data communication on multipoint bus-transmission lines. The SN65LBC176A-EP is designed for balanced

transmission lines and is compatible with ANSI standard TIA/EIA-485-A and ISO 8482. The SN65LBC176A-EP

offers improved switching performance over its predecessors without sacrificing significantly more power.

The SN65LBC176A-EP combines a 3-state, differential line driver and a differential input line receiver, both of

which operate from a single 5-V power supply. The driver and receiver have active-high and active-low enables,

respectively, which can externally connect together to function as a direction control. The driver differential

outputs and the receiver differential inputs connect internally to form a differential input/output (I/O) bus port that

is designed to offer minimum loading to the bus whenever the driver is disabled or VCC = 0. This port features

wide positive and negative common-mode voltage ranges, making the device suitable for party-line

applications. Low device supply current can be achieved by disabling the driver and the receiver.

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