描述 Description

These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. These devices are particularly suitable for implementing multiuser registers, I/O ports, bidirectional bus drivers, and working registers.
With the clock-enable () input low, the eight D-type edge-triggered flip-flops enter data on the low-to-high transitions of the clock (CLK) input. Taking high disables the clock buffer, latching the outputs. These devices have noninverting data (D) inputs. Taking the clear () input low causes the eight Q outputs to go low independently of the clock.
Multiuser buffered output-enable (,, and ) inputs can be used to place the eight outputs in either a normal logic state (high or low logic level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.
The output enables do not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
The SN54AS825A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74AS825A is characterized for operation from 0°C to 70°C.
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= H if any of OE1\\, OE2\\, or OE3\\ are high.= L if all of OE1\\, OE2\\, or OE3\\ are low.

特性 Features

? Functionally Equivalent to AMD's AM29825
? Improved IOH Specifications
? Multiple Output Enables Allow Multiuser Control of theInterface
? Outputs Have Undershoot-Protection Circuitry
? Power-Up High-Impedance State
? Buffered Control Inputs Reduce dcLoading Effects
? Package Options Include Plastic Small-Outline (DW) Packages,Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic(JT) 300-mil DIPs