描述 Description

The Si5323 jitter attenuator combines third-generation DSPLL technology to enable any-frequency clock generation and jitter attenuation for applications requiring a high level of jitter performance. This device supports 2 input(s), 2 output(s) and has a maximum frequency output of 1050 MHz. The Si5323 delivers 0.3 ps rms phase jitter performance with 0 ppm error. The loop filter is fully integrated on-chip, eliminating the risk of noise coupling associated with discrete solutions. Further, the jitter attenuation bandwidth is digitally programmable, providing jitter performance optimization at the application level.

簡(jiǎn)介

Si5323屬于集成電路（IC）的時(shí)鐘發(fā)生器PLL頻率合成器。由制造生產(chǎn)的Si5323時(shí)鐘發(fā)生器，PLL，頻率合成器時(shí)鐘發(fā)生器、PLL 和頻率合成器集成電路 (IC) 可為邏輯器件提供參考信號(hào)的穩(wěn)定定時(shí)脈沖，這些器件包括計(jì)算機(jī)、微控制器、數(shù)據(jù)通信系統(tǒng)和圖形/視頻發(fā)生器。這些集成電路可能包括緩沖器、驅(qū)動(dòng)器、分頻器、倍頻器、多路復(fù)用器、合成器、扇出分配器和預(yù)分頻器。