General description

The SDA 9380 is a highly integrated deflection controller and RGB video processor for CTV receivers with 15 to 19kHz or 31 to 38kHz line frequencies. The deflection component controls among others an horizontal drive2001-01-29r circuit for a flyback line output stage, a DC coupled vertical sawtooth output stage and an East-West raster correction circuit. All adjustable output parameters are I2C-Bus controlled. Inputs are HSYNC and VSYNC. The HSYNC signal is the reference for the internal clock system which includes the=Φ1=and Φ2=control loops.

The RGB processor has two YUV/RGB inputs and one RGB input. One YUV/RGB input and the RGB input are for SVGA and text/OSD with fast blanking. The RGB output stage has two control loops for cut off and white level with halt capability in vertical shrink modes. An overall Y output and an adjustable delay of the RGB outputs related to this signal are suitable for a scan velocity modulation circuit.

The supply voltages of the IC are 3.3V and 8V. It is mounted in a P-MQFP package with 64 pins.