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SC28L194A1A

Quad UART for 3.3V and 5V supply voltage

DESCRIPTION ThePhilips28L194QuadUARTisasinglechipCMOS-LSIcommunicationsdevicethatprovides4full-duplexasynchronouschannelswithsignificantlydeeper16byteFIFOs,Automaticin-bandflowcontrolusingXon/XoffcharactersdefinedbytheuserandaddressrecognitionintheWake-upm

SC28L194A1A

Quad UART for 3.3 V and 5 V supply voltage; Single 3.3V and 5.0V power supply\nFour Philips industry standard full duplex UART channels\nSixteen byte receiver FIFOs for each UART\nSixteen byte transmit FIFOs for each UART\nIn band flow control using programmable Xon/Xoff characters\nFlow control using CTSN RTSN hardware handshaking\nAutomatic address detection in multi-drop mode\nThree byte general purpose character recognition\nFast data bus, 15 ns data bus release time, 125 ns bus cycle time\nProgrammable interrupt priorities\nAutomatic identification of highest priority interrupt pending\nGlobal interrupt and control registers ease setup and interrupt handling\nVectored interrupts with programmable interrupt vector formats Interrupt vector modified with channel number\nInterrupt vector modified with channel number and channel type\nInterrupt vector not modified\nIACKN and DACKN signal pins\nWatch dog timer for each receiver (64 receive clock counts)\nProgrammable Data Formats: 5 to 8 data bits plus parity\nOdd, even force or no parity\n1, 1.5 or 2 stop bits\nFlexible baud rate selection for receivers and transmitters: 22 fixed rates; 50 - 230.4K baud or 100 to 460.8K baud\nAdditional non-standard rates to 500K baud with internal generators\nTwo reload-counters provide additional programmable baud rate generation\nExternal 1x or 16x clock inputs\nSimplified baud rate selection\n1 MHz 1x and 16x data rates full duplex all channels.\nParity, framing and overrun error detection\nFalse start bit detection\nLine break detection and generation\nProgrammable channel mode Normal(full duplex)\nDiagnostic modes \nautomatic echo \nlocal loop back \nremote loop back\n\nFour I/O ports per UART for modem controls, clocks, RTSN, I/O, etc. All I/O ports equipped with 'Change of State Detectors'\nTwo global inputs and two global outputs for general purpose I/O\nPower down mode\nOn chip crystal oscillator, 2-8 MHz\nTTL input levels. Outputs switch between full V CC and V SS\nHigh speed CMOS technology\n80-pin Low Profile Quad Flat Pack LQFP and 68-pin PLCC\n;

The Philips 28L194 Quad UART is a single chip CMOS-LSI communications device that provides 4 full-duplex asynchronous channels with significantly deeper 16 byte FIFOs, Automatic in-band flow control using Xon/Xoff characters defined by the user and address recognition in the Wake-up mode. Synchronous bus interface is used for all communication between host and QUART. It is fabricated in Philips state of the art CMOS technology that combines the benefits of low cost, high density and low power consumption.\nThe operating speed of each receiver and transmitter can be selected independently from one of 22 fixed baud rates, a 16X clock derived from one of two programmable baud rate counters or one of three external 16X clocks (1 available at 1x clock rate). The baud rate generator and counter can operate directly from a crystal or from seven other external or internal clock inputs. The ability to independently program the operating speed of the receiver and transmitter makes the Quad UART particularly attractive for dual speed full duplex channel applications such as clustered terminal systems. The receivers and transmitters are buffered with FIFOs of 16 characters to minimize the potential for receiver overrun and to reduce interrupt overhead. In addition, a handshaking capability and in-band flow control are provided to disable a remote UART transmitter when the receiver buffer is full or nearly so.\nTo minimize interrupt overhead an interrupt arbitration system is included which reports the context of the interrupting UART via direct access or through the modification of the interrupt vector. The context of the interrupt is reported as channel number, type of device interrupting (receiver COS etc.) and, for transmitters or receivers, the fill level of the FIFO.\nThe Quad UART provides a power down mode in which the oscillator is stopped but the register contents are maintained. This results in reduced power consumption of several orders of magnitudes. The Quad UART is fully TTL compatible when operating from a single +5V or 3.3V power supply. Operation at 3.3V or 5.0V is maintained with CMOS interface levels.\n

SC28L194A1BE

QuadUARTfor3.3Vand5Vsupplyvoltage

DESCRIPTION ThePhilips28L194QuadUARTisasinglechipCMOS-LSIcommunicationsdevicethatprovides4full-duplexasynchronouschannelswithsignificantlydeeper16byteFIFOs,Automaticin-bandflowcontrolusingXon/XoffcharactersdefinedbytheuserandaddressrecognitionintheWake-upm