描述 Description

The DSC SAA8122A is a high performance, low power, single-chip Million Instructions Per Second (MIPS) based signal processor, part of the ImagIC family, which is dedicated to image processing, compression, formatting and storage. The DSC SAA8122A is optimized for use with Philips range of CCDs (e.g: FXA1022, 2 Mpixels CCD), V-driver (TDA9991), CDS/PGA/ADC (TDA9952), allowing easy implementation of a complete system solution and fast development of high performance consumer digital still cameras.

特性 Features

General

■ Supports a wide range of progressive CCDs (VGA, SVGA, QGA, XGA, EQGA), with RGB Bayer filters up to 2 Mpixels

■ Performs an advanced RGB to YUV conversion

■ Includes a smart measurement unit to speed up the control loop (focus, auto white balance, etc.)

■ Supports a wide range of LCD and TV formats (both NTSC and PAL) with text insertion features

■ Includes an embedded JPEG encoder/decoder unit

■ Includes a MIPS PR3001 CPU, running at a frequency in a range from 12 to 28 MHz

■ PRISC compatible PI-bus architecture, interrupt, power management, clock and reset architectures

■ Includes a dedicated video bus supporting SDRAM memory for picture storage

■ Interface to ROM, DRAM, SRAM, flash and PC Card [Compact Flash and SSFDC (SmartMedia)]

■ Integrated general purpose peripheral units like a UART, timers, an I2C-bus transceiver, ADC converters, RTC and I/O ports

■ Includes USB and RS-232C communication interfaces.

External interfaces

■ Two UART (RS-232) data ports with DMA capabilities (≤187.5 kbit/s) including hardware flow control RxD, TxD, RTS, CTS for modem support

■ 32 general purpose, bidirectional I/O interface pins, the first 8 bits may also be used as interrupt inputs

■ Two PWM outputs (8-bit resolution).

CPU related features

■ 32-bit PR3001 core

■ 1-kbyte data cache and 4-kbyte instruction cache

■ Programmable low-power mode, including wake-up on interrupt

■ Memory management unit [Translation Lookaside Buffer (TLB)]

■ Two built in 24-bit general purpose timers and one 24-bit watchdog timer

■ Real-time clock unit (active in sleep mode)

■ On-chip 8-kbyte SRAM for storing code which needs fast execution

■ Platform software based on real-time pSOS (plug-in Silicon Operating System).

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