最新无码a∨在线观看,一本av高清一区二区三区,亚洲熟妇色l20p,宅男噜噜69av,中出あ人妻熟女中文字幕

首頁(yè)>SAA7206>規(guī)格書詳情

SAA7206中文資料飛利浦?jǐn)?shù)據(jù)手冊(cè)PDF規(guī)格書

SAA7206
廠商型號(hào)

SAA7206

功能描述

DVB compliant descrambler

文件大小

193.8 Kbytes

頁(yè)面數(shù)量

52 頁(yè)

生產(chǎn)廠商 Philips Semiconductors
企業(yè)簡(jiǎn)稱

PHI飛利浦

中文名稱

荷蘭皇家飛利浦

數(shù)據(jù)手冊(cè)

下載地址一下載地址二

更新時(shí)間

2025-7-27 14:01:00

人工找貨

SAA7206價(jià)格和庫(kù)存,歡迎聯(lián)系客服免費(fèi)人工找貨

SAA7206規(guī)格書詳情

GENERAL DESCRIPTION

The SAA7206H (DVB compliant) is designed for use in MPEG-2 based digital TV receivers, incorporating conditional access filters. Such receivers are to be implemented in, for instance, a digital video broadcasting top set box, or an integrated digital TV receiver.

FEATURES

? Input data fully compliant with the Transport Stream (TS) definition of the MPEG-2 systems specification

? Input data signals; [Forward Error Correction (FEC) Interface]

– modem data input bus (8-bit wide)

– valid input data indicator

– erroneous packet indicator

– first packet byte indicator

– byte strobe signal (for asynchronous mode only).

The interface can be programmed to one of two modes:

– Asynchronous mode; byte strobe input signal (MBCLK) < 9 MHz, for connection to a modem (FEC)

– Synchronous mode; MBCLK is not used. Data is delivered to the descrambler synchronized with the chip clock (DCLK) [9 MHz (typ.) with a 33 duty cycle].

? No external memory

? Effective bit rate; fbit ≤ 72 MHz

? Control interface; 8-bit multiplexed data/address, memory mapped I/O (90CE201 microcontroller parallel bus compatible), in combination with a microcontroller interrupt signal (IRQ)

? Output ports are identical to the input data interface (demultiplexer interface)

– except for the packet error indicator (MB/MB), as the descrambler translates an active MB signal to the ‘transport_error_indicator’ bit in the transport stream

– except for the byte strobe input signal (MBCLK), as data is delivered to the demultiplexer, synchronized with the descrambler chip clock which is generated by the demultiplexer

? Descrambler, based on the super descrambler mechanism algorithm with stream decipher and block decipher. The descrambler is initialized with a 64-bit Control Word (CW) at the beginning of a transport stream packet payload of a selected Packet Identification (PID). The descrambler operates on transport stream packet or Packetized Elementary Stream (PES) packet payloads

? Microcontroller support; only for control, no specific descrambling tasks are performed by the microcontroller. However, parsing and processing of conditional access information (such as EMM and ECM data) is left to the system microcontroller

? Boundary scan test port for boundary scan.

供應(yīng)商 型號(hào) 品牌 批號(hào) 封裝 庫(kù)存 備注 價(jià)格
PHI
24+
QFP
6868
原裝現(xiàn)貨,可開13%稅票
詢價(jià)
PHI
24+
47395
詢價(jià)
PHI
2407+
QFP
7750
原裝現(xiàn)貨!實(shí)單直說(shuō)!特價(jià)!
詢價(jià)
PHI
23+
N A
11200
原廠授權(quán)一級(jí)代理、全球訂貨優(yōu)勢(shì)渠道、可提供一站式BO
詢價(jià)
PHI
2447
QFP
100500
一級(jí)代理專營(yíng)品牌!原裝正品,優(yōu)勢(shì)現(xiàn)貨,長(zhǎng)期排單到貨
詢價(jià)
PHI
23+
QFP
50000
全新原裝正品現(xiàn)貨,支持訂貨
詢價(jià)
PHI
23+
QFP
2870
絕對(duì)全新原裝!現(xiàn)貨!特價(jià)!請(qǐng)放心訂購(gòu)!
詢價(jià)
PHI
2138+
QFP
8960
專營(yíng)BGA,QFP原裝現(xiàn)貨,假一賠十
詢價(jià)
PHI
24+
QFP64
39197
鄭重承諾只做原裝進(jìn)口現(xiàn)貨
詢價(jià)
PHI
23+24
QFP
29850
原裝正品優(yōu)勢(shì)渠道價(jià)格合理.可開13%增值稅發(fā)票
詢價(jià)