INTRODUCTION

The S6B0796 is a 240-outputs segment/common driver LSI for graphic dot-matrix liquid crystal display systems. It is fabricated by low power CMOS high voltage process technology. This device consists of 240-bits bi-directional shift register, 240-bits data latch and 240-bits driver. In case of segment mode, the data input is selected 4bit parallel input mode and 8bit parallel input mode by a mode (MD) pin. In case of common mode, data input/output pins are bi-directional, four data shift directions are pin-selectable.

FEATURES

Both Segment Mode and Common Mode

- Supply voltage for LC driver: +15.0 to +32.0V

- Number of LC driver outputs: 240

- Low output impedance

- Low power consumption

- Supply voltage for the logic system: +2.4V to +5.5V

- CMOS silicon gate process (P-type Silicon Substrate)

- Package: 268-pin TCP (Tape Carrier Package) or Gold bumped chip

Segment Mode

- Shift clock frequency: 20MHz (Max) (Vdd=+5V±10) 12MHz (Max) (Vdd=+2.4V to +4.5V)

- Adopts a data bus system

- 4- / 8-bit parallel input modes are selectable with a mode (MD) pin

- Automatic transfer function of an enable signal

- Automatic counting function which, in the chip select, causes the internal clock to be stopped by automatically counting 240 of input data

- Line latch circuit reset function when DISPOFFB active

Common Mode

- Shift clock frequency: 4.0MHz (Max) (vdd=+2.4V to +5.5V)

- Built-in 240-bits bi-directional shift register (divisible into 120-bits ′2)

- Available in a single mode (240-bits shift register) or in a dual mode (120-bits shift register ′2)

- Shift register circuit reset function when DISPOFFB active