描述 Description

PMC-Sierra’s RM7065A is a highly integrated symmetric superscalar microprocessor capable of issuing two instructions each processor cycle. It has two high-performance 64-bit integer units as well as a high-throughput, fully pipelined 64-bit floating point unit.

特性 Features

? Dual issue symmetric superscalar microprocessor with instruction prefetch optimized for system level price/performance

? 300, 350 MHz operating frequency

? >525 Dhrystone 2.1 MIPS @ 350 MHz

? High-performance system interface

? 1000 MB per second peak throughput

? 125 MHz max. freq., multiplexed address/data

? Supports two outstanding reads with out-of-order return

? Processor clock multipliers 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9

? Integrated primary and secondary caches

? All are 4-way set associative with 32 byte line size

? 16 KB instruction, 16 KB data, 256 KB on-chip secondary

? Per line cache locking in primaries and secondary

? Fast Packet Cache? increases system efficiency in networking applications

? High-performance floating-point unit — 800 MFLOPS maximum

? Single cycle repeat rate for common single-precision operations and some double-precision operations

? Single cycle repeat rate for single-precision combined multiply-add operations

? Two cycle repeat rate for double-precision multiply and double-precision combined multiply-add operations

? MIPS IV superset instruction set architecture

? Data PREFETCH instruction allows the processor to overlap cache miss latency and instruction execution

? Single-cycle floating-point multiply-add

? Integrated memory management unit

? Fully associative joint TLB (shared by I and D translations)

? 64/48 dual entries map 128/96 pages

? Variable page size

? Embedded application enhancements

? Specialized DSP integer Multiply-Accumulate instructions, (MAD/MADU) and three-operand multiply instruction (MUL)

? I&D Test/Break-point (Watch) registers for emulation & debug

? Performance counter for system and software tuning & debug

? Fourteen fully prioritized vectored interrupts — 10 external, 2 internal, 2 software

? Fully static CMOS design with dynamic power down logic