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RM5231集成電路(IC)的微處理器規(guī)格書PDF中文資料

RM5231
廠商型號

RM5231

參數(shù)屬性

RM5231 包裝為散裝;類別為集成電路(IC)的微處理器;產(chǎn)品描述:MIPS PROCESSOR - 32-BIT SYSAD -

功能描述

RM5231??Microprocessor with 32-Bit System Bus Data Sheet Released

文件大小

630.34 Kbytes

頁面數(shù)量

39

生產(chǎn)廠商

PMC

網(wǎng)址

網(wǎng)址

數(shù)據(jù)手冊

下載地址一下載地址二

更新時(shí)間

2025-9-1 15:53:00

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RM5231規(guī)格書詳情

Hardware Overview

The RM5231 offers a high-level of integration targeted at high-performance embedded applications. The key elements of the RM5231 are briefly described in this section.

特性 Features

? Dual Issue superscalar microprocessor

? 150, 200, & 250 MHz operating frequencies

? 300 Dhrystone2.1 MIPS

? System interface optimized for embedded applications

? 32-bit system interface lowers total system cost

? High-performance write protocols maximize uncached write bandwidth

? Processor clock multipliers: 2, 2.5, 3, 3.5, 4, 4.5, 5, 6, 7, 8, 9

? 2.5 V core with 3.3 V IOs

? IEEE 1149.1 JTAG boundary scan

? Integrated on-chip caches

? 32 KB instruction and 32 KB data — 2 way set associative

? Per set locking

? Virtually indexed, physically tagged

? Write-back and write-through on a per page basis

? Pipeline restart on first doubleword for data cache misses

? Integrated memory management unit

? Fully associative joint TLB (shared by I and D translations)

? 48 dual entries map 96 pages

? Variable page size (4 KB to 16 MB in 4x increments)

? High-performance floating-point unit — up to 500 MFLOPS

? Single cycle repeat rate for common single-precision operations and some double precision operations

? Two cycle repeat rate for double-precision multiply and double precision combined multiply-add operations

? Single cycle repeat rate for single-precision combined multiply-add operation

? MIPS IV instruction set

? Floating point multiply-add instruction increases performance in signal processing and graphics applications

? Conditional moves to reduce branch frequency

? Index address modes (register + register)

? Embedded application enhancements

? Specialized DSP integer Multiply-Accumulate instructions and 3-operand multiply instruction

? I and D cache locking by set

? Optional dedicated exception vector for interrupts

? Fully static 0.25 micron CMOS design with power down logic

? Standby reduced power mode with WAIT instruction

? 2.5 V core with 3.3 V I/O

? 128-pin Power-Quad 4 (QFP) package

產(chǎn)品屬性

  • 產(chǎn)品編號:

    RM5231A-350P-B002

  • 制造商:

    Microchip Technology

  • 類別:

    集成電路(IC) > 微處理器

  • 包裝:

    散裝

  • 核心處理器:

    MIPS RISC

  • 內(nèi)核數(shù)/總線寬度:

    1 核,64 位

  • 速度:

    350MHz

  • RAM 控制器:

    SDRAM

  • 圖形加速:

  • 電壓 - I/O:

    2.5V,3.3V

  • 描述:

    MIPS PROCESSOR - 32-BIT SYSAD -

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