DESCRIPTION

The PZ3032 CPLD (Complex Programmable Logic Device) is the first in a family of Fast Zero Power (FZP?) CPLDs from Philips Semiconductors. These devices combine high speed and zero power in a 32 macrocell CPLD. With the FZP? design technique, the PZ3032 offers true pin-to-pin speeds of 8ns, while simultaneously delivering power that is less than 35μA at standby without the need for ‘turbo bits’ or other power down schemes. By replacing conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates, the dynamic power is also substantially lower than any competing CPLD – 70 lower at 50MHz.

FEATURES

? Industry’s first TotalCMOS? PLD – both CMOS design and process technologies

? Fast Zero Power (FZP?) design technique provides ultra-low power and very high speed

? High speed pin-to-pin delays of 8ns

? Ultra-low static power of less than 35μA

? Dynamic power that is 70 lower at 50MHz than competing devices

? 100 routable with 100 utilization while all pins and all macrocells are fixed

? Deterministic timing model that is extremely simple to use

? 2 clocks with programmable polarity at every macrocell

? Support for complex asynchronous clocking

? Innovative XPLA? architecture combines high speed with extreme flexibility

? 1000 erase/program cycles guaranteed

? 20 years data retention guaranteed

? Logic expandable to 37 product terms

? PCI compliant

? Advanced 0.5μ E2CMOS process

? Security bit prevents unauthorized access

? Design entry and verification using industry standard and Philips CAE tools

? Reprogrammable using industry standard device programmers

? Innovative Control Term structure provides either sum terms or product terms in each logic block for:

– Programmable 3-State buffer

– Asynchronous macrocell register preset/reset

? Programmable global 3-State pin facilitates ‘bed of nails’ testing without using logic resources

? Available in both PLCC and TQFP packages