1 Features

? 2-V to 5.5-V VCC operation

? Maximum tpd of 7.1 ns at 5 V

? Typical VOLP (output ground bounce)

< 0.8 V at VCC = 3.3 V, TA = 25°C

? Typical VOHV (output VOH undershoot)

> 2.3 V at VCC = 3.3 V, TA = 25°C

? Support mixed-mode voltage operation on all ports

? 8-bit serial-in, parallel-out shift

? Ioff supports live insertion, partial power-down

mode, and back-drive protection

? Shift register has direct clear

? Latch-up performance exceeds 250 mA per JESD

17

2 Applications

? Output expansion

? LED matrix control

? 7-segment display control

3 Description

The SN74LV595A device contains an 8-bit serial-in,

parallel-out shift register that feeds an 8-bit D-type

storage register. Both the shift register clock (SRCLK)

and storage register clock (RCLK) are positive-edge

triggered.