描述 Description

FEATURES
? Monolithic device integrating eight T1/J1 or E1 short haul line interface units.
? Software switchable between T1/J1 and E1 operation on a per-device basis.
? Meets or exceeds T1/J1 and E1 short haul network access specifications including ANSI T1.102, T1.403, T1.408, AT&T TR 62411, ITU-T G.703, G.704 as well as ETSI 300-011, TBR 4, TBR 12, and TBR 13. In conjunction with the TEMAP 84 (PM5366), allows Add Drop Multiplexers and Terminal Multiplexers to meet GR253, GR496, and G.783.
? Optional encoding/decoding of B8ZS, HDB3, and AMI line codes.
? Provides receive equalization, clock recovery, and line performance monitoring.
? Provides transmit and receive jitter attenuation.
? Provides digitally programmable pulse templates.
? Provides a selectable, per channel independent de-jittered T1 or E1 recovered clock for system timing and redundancy.
? Provides PRBS generators and detectors on each tributary for error testing at DS1 and E1 rates as recommended in ITU-T O.151.
? Uses line rate system clock.

特性 Features

? Monolithic device integrating eight T1/J1 or E1 short haul line interface units.
? Software switchable between T1/J1 and E1 operation on a per-device basis.
? Meets or exceeds T1/J1 and E1 short haul network access specifications including ANSI T1.102, T1.403, T1.408, AT&T TR 62411, ITU-T G.703, G.704 as well as ETSI 300-011, TBR 4, TBR 12, and TBR 13. In conjunction with the TEMAP 84 (PM5366), allows Add Drop Multiplexers and Terminal Multiplexers to meet GR253, GR496, and G.783.
? Optional encoding/decoding of B8ZS, HDB3, and AMI line codes.
? Provides receive equalization, clock recovery, and line performance monitoring.
? Provides transmit and receive jitter attenuation.
? Provides digitally programmable pulse templates.
? Provides a selectable, per channel independent de-jittered T1 or E1 recovered clock for system timing and redundancy.
? Provides PRBS generators and detectors on each tributary for error testing at DS1 and E1 rates as recommended in ITU-T O.151.
? Uses line rate system clock.
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