描述 Description

The PLA133-97 is an advanced fanout buffer designed for automotive high performance, low-power, small form factor applications. The PLA133-97 accepts a reference clock input from DC to 150 MHz and provides nine outputs of the same frequency with ultra-low additive jitter. The device is AEC-Q100 qualified. The PLA133-97 is offered in a small 3 mm x 3 mm wettable flank QFN-16L package.

The PLA133-97 outputs can be disabled to a high impedance (tri-state) by pulling low the OE pin. When the OE pin is high, the outputs are enabled and follow the REF input signal. When the OE pin is left open, a pull-up resistor on the chip will default the OE pin to logic 1 so the outputs are enabled.

CLK8 is a free running output that remains enabled when the OE pin is pulled low.

6-output PLA133-67 https://www.microchip.com/wwwproducts/en/PLA133-67? and 4 output PLA133-47 https://www.microchip.com/wwwproducts/en/PLA133-47 are also available.

特性 Features

? Automotive AEC-Q100 Qualified
? 1:9 LVCMOS Output Fanout Buffer from DC to150 MHz
? Low Additive Phase Jitter of 60 fs RMS
? 8 mA Output Drive Strength
? Automotive Applications Grade 1 Compliant
? Low Input-Output Delay
? Output-Output Skew <250 ps
? 2.5V to 3.3V, ±10% Operation
? 1.8V ±5% Operation up to 67 MHz
? Wide Temperature Range: –40°C to +125°C
? Available in 16-Pin wettable flank QFN Package
Automotive Applications
? ADAS Vision System
? Infotainment and Dashboard

簡介

PLA133-97屬于集成電路（IC）的時鐘發(fā)生器PLL頻率合成器。由制造生產的PLA133-97時鐘發(fā)生器，PLL，頻率合成器時鐘發(fā)生器、PLL 和頻率合成器集成電路 (IC) 可為邏輯器件提供參考信號的穩(wěn)定定時脈沖，這些器件包括計算機、微控制器、數據通信系統(tǒng)和圖形/視頻發(fā)生器。這些集成電路可能包括緩沖器、驅動器、分頻器、倍頻器、多路復用器、合成器、扇出分配器和預分頻器。