描述 Description

The PL138-48 family is a high performance low-cost 1:4 outputs Differential LVPECL fanout buffer.The family of Differential LVPECL buffers are designed to operate from a single power supply of 2.5V±5% or 3.3V±10%. The differential input pairs are designed to accept most standard input signal levels, using an appropriate resistor bias network, and produce a high quality set of outputs with the lowest possible skew on the outputs, which is guaranteed for part-to-part or lot-to lot skew.Designed to fit in a small form-factor package, PL138 family offers up to 1GHz of output operation with very low-power consumption, and lowest additive jitter of any comparable device. The Output Enable feature, when activated, allows the IC to consume less than 10μA of current.

特性 Features

? Four differential 2.5V/3.3V LVPECL output pairs
? Output Frequency: ≤1GHz
? Two selectable differential input pairs
? Translates any standard single-ended or differential input format to LVPECL output. It can accept the following standard input formats and more:
? LVPECL, LVCMOS, LVDS, HCSL, SSTL, LVHSTL, CML
? Output Skew: 25ps (typ.)
? Part-to-part skew: 140ps (typ.)
? Propagation delay: 1.5ns (typ.)
? Additive Jitter: <100fs (typ.)
? Operating Supply Voltage: 2.375V ~ 3.63V
? Operating temperature range from -40°C to 85°C
? Package availability: 20-pin TSSOP

簡介

PL138-48屬于集成電路（IC）的時(shí)鐘緩沖器驅(qū)動器。由制造生產(chǎn)的PL138-48時(shí)鐘緩沖器，驅(qū)動器時(shí)鐘緩沖器和驅(qū)動器集成電路產(chǎn)品族中的產(chǎn)品用于幫助信號在系統(tǒng)中傳輸，常用作頻率/時(shí)間參考信號，以同步系統(tǒng)內(nèi)的活動。盡管這些器件最常用到的功能就是緩沖（即，為使信號不受驅(qū)動負(fù)載的影響而從某個信號源復(fù)制信號），但是該產(chǎn)品族中的某些器件還能執(zhí)行其他功能，例如選擇性改變緩沖信號路徑、按某個整數(shù)值分割信號頻率，或進(jìn)行所用電信號格式轉(zhuǎn)換。