ExpressLane? PCI Express to PCI Bridge

特性 Features

General Features

o Forward and Reverse bridging

o 144-ball BGA package with standard 1.0 mm pitch (13mm x 13mm)

o Alternative fine-pitch BGA package(10mm x 10mm)

o Low power – 400 milliwatts

o EEPROM configuration option with SPI

o Internal 8Kbyte shared RAM

o 1.5 V core supply voltage

o JTAG

o Four (4) GPIO pins for maximum design flexibility

o Extensive PME support including D0 and D0Active, D1, D2 and D3 Hot and D3 Cold

o Lead-free packaging available ? Integrated PCI Express Interface

o PCI Express Base 1.0a compliant

o x1 Link, dual-simplex, 2.5 Gbps per direction

o One virtual channel

o Automatic LVDS polarity reversal

o 128 byte maximum payload size

o Link CRC

o Link power management

o Flow control buffering

o PCI Express transaction queues for eight (8) outstanding TLPs

PCI Interface

o PCI v.3.0: 32 bits, up to 66 MHz

o PCI Power Management 1.1

o Internal arbiter supports up to 4 external masters; REQ#/GNT# signals

o 3.3V I/O and 5V tolerant PCI

o Message Signal Interrupt (MSI) support

o Provides PCI clock output

o Four mailbox registers for messaging

o VGA and ISA Enable registers for legacy operation