PEB20570中文資料英飛凌數(shù)據(jù)手冊(cè)PDF規(guī)格書(shū)
| 廠商型號(hào) |
PEB20570 |
| 功能描述 | DSP Embedded Line and Port Interface Controller |
| 文件大小 |
170.77 Kbytes |
| 頁(yè)面數(shù)量 |
8 頁(yè) |
| 生產(chǎn)廠商 | Infineon |
| 中文名稱 | 英飛凌 |
| 網(wǎng)址 | |
| 數(shù)據(jù)手冊(cè) | |
| 更新時(shí)間 | 2025-9-7 15:22:00 |
| 人工找貨 | PEB20570價(jià)格和庫(kù)存，歡迎聯(lián)系客服免費(fèi)人工找貨 |
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更多PEB20570規(guī)格書(shū)詳情
Addendum to “DELIC Clock System Synchronization”
The DELIC Clock System Synchronization is described in the DELIC-LC PEB 20570/DELIC-PB PEB 20571 Data Sheet, independent of the version (2.1 .. 3.1).
As an addendum to chapter “DELIC Clock System Synchronization” of the DELICLC/DELIC-PB Data Sheet the following describes the system behaviour when using the VIP PEB 20590 or PEB 20591 in LT-T mode, for example when synchronizing to the Central Office.
When the Central Office is activated, its clock signal is retrieved by the RxPLL of the VIP and a 1.536 MHz reference signal is generated and used as input signal for the DELIC DCXO (pin XCLK). This signal is divided down to 8 kHz and used as input for the DCXO phase detector (PD). The second input to PD is another 8 kHz signal which originates from the 16.384 MHz output of the DCXO.
The DELIC PLL multiplies the 16.384 MHz DCXO signal up to 61.44 MHz. A divider generates the 15.36 MHz layer 1 clock which is used to clock the VIP.
產(chǎn)品屬性
- 型號(hào)：
PEB20570
- 制造商：
INFINEON
- 制造商全稱：
Infineon Technologies AG
- 功能描述：
DSP Embedded Line and Port Interface Controller
| 供應(yīng)商 | 型號(hào) | 品牌 | 批號(hào) | 封裝 | 庫(kù)存 | 備注 | 價(jià)格 |
|---|---|---|---|---|---|---|---|
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24+ |
QFP100 |
80000 |
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詢價(jià) | ||
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QFP100 |
8500 |
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85600 |
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62 |
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TQFP100 |
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INF |
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詢價(jià) | ||
Infineon Technologies |
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原裝 |
5000 |
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詢價(jià) | ||
infineon |
QFP-100 |
68500 |
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