描述 Description

The PCU9669 is an advanced single master mode I2C-bus controller. It is a fourth generation bus controller designed for data intensive I2C-bus data transfers. It has three independent I2C-bus channels, one of them with data rates up to 1 Mbits/s using the Fast-mode Plus (Fm+) open-drain topology and two with a much larger transmit only transfer rate of up to 5 Mbits/s using the new Ultra Fast-mode (UFm) bus with push-pull topology. Each channel has a generous 4352 byte data buffer which makes the PCU9669 the ideal companion to any CPU that needs to transmit and receive large amounts of serial data with minimal interruptions.
The PCU9669 is a 8-bit parallel-bus to I2C-bus protocol converter. It can be configured to communicate with up to 64 slaves in one serial sequence with no intervention from the CPU. The controller also has a sequence loop control feature that allows it to automatically retransmit a stored sequence.
Its onboard oscillator and PLL allow the controller to generate the clocks for the I2C-bus and for the interval timer used in sequence looping. This feature greatly reduces CPU overhead when data refresh is required in fault tolerant applications.
An external trigger input allows data synchronization with external events. The trigger signal controls the rate at which a stored sequence is re-transmitted over the I2C-bus.
Error reporting is handled at the transaction level, channel level, and controller level. A simple interrupt tree and interrupt masks allow further customization of interrupt management.
The controller parallel bus interface runs at 3.3 V and the I2C-bus I/Os logic levels are referenced to a dedicated VDD(IO) input pin with a range of 3.0 V to 5.5 V.

特性 Features

? Parallel-bus to I2C-bus protocol converter and interface
? 5 Mbit/s unidirectional data transfer on Ultra Fast-mode (UFm) channel (push-pull driver)
? 1 Mbit/s and up to 30 mA SCL/SDA IOL Fast-mode Plus (Fm+) capability
? Internal oscillator trimmed to 1 % accuracy reduces external components
? Individual 4352-byte buffers for the Fm+ and UFm channels for a total of 13056 bytes of buffer space
? Three levels of reset: individual software channel reset, global software reset, global hardware RESET pin
? Communicates with up to 64 slaves in one serial sequence
? Sequence looping with interval timer
? Supports SCL clock stretching (Fm+ only)
? JTAG port available for boundary scan testing during board manufacturing process
? Trigger input synchronizes serial communication exactly with external events
? Maskable interrupts
? Fast-mode Plus I2C-bus capable and compatible with SMBus
? Operating supply voltage: 3.0 V to 3.6 V (device and host interface)
? I2C-bus I/O supply voltage: 3.0 V to 5.5 V
? Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
? ESD protection exceeds 8000 V HBM per JESD22-A114 and 1000 V CDM per JESD22-C101
? Packages offered: LQFP48

應(yīng)用 Application

添加I2C總線端口至沒(méi)有此類(lèi)端口的控制器/處理器
添加額外的I2C總線端口至需要多個(gè)I2C總線端口的控制器/處理器
將8位并行數(shù)據(jù)轉(zhuǎn)換成串行數(shù)據(jù)流，以避免在整個(gè)印刷電路板上排布大量的走線
娛樂(lè)系統(tǒng)
LED矩陣控制
數(shù)據(jù)密集型I2C總線傳送