描述 Description

The dual-core P5020 and single-core P5010 processors deliver 64-bit processing, based on the e5500 core built on Power Architecture? technology. With frequencies scalable to 2.0 GHz, large caches and high per-cycle efficiency, these products target control plane and computer applications that require high single-threaded performance.
The P5 platform leverages architectural features pioneered in the P4 platform, including the three-level cache hierarchy for low latencies, hardware hypervisor for robust virtualization support, data path acceleration architecture (DPAA) for offloading packet handling tasks from the core and the CoreNet? switch fabric that eliminates internal bottlenecks. This enables architectural compatibility from the P5 platform to the P4 platform as well as to the P3 platform.

特性 Features

Core Complex
? Single or dual 64-bit e5500 cores offered at 2.0 GHz
? Three level cache-hierarchy: 32 KB I/D L1; 512 KB private L2 per core; 2 MB shared L3
? Up to 2.0 GHz with 64-bit ISA support (Power Architecture v2.06-compliant)
? Three levels of instruction: user, supervisor, hypervisor
? Hybrid 32-bit mode to support legacy software and transition to 64-bit architecture
? 2.0 MB configures as dual 1 MB platform cache