MX25U51245GXDI0A屬于集成電路（IC）的存儲(chǔ)器。由旺宏電子股份有限公司制造生產(chǎn)的MX25U51245GXDI0A存儲(chǔ)器存儲(chǔ)器是集成電路上用作數(shù)據(jù)存儲(chǔ)設(shè)備的半導(dǎo)體器件。這些器件分為非易失性或易失性兩種，格式包括 CBRAM、DRAM、EEPROM、EERAM、EPROM、閃存、FRAM、NVSRAM、PCM (PRAM)、PSRAM、RAM 和 SRAM。這些器件的存儲(chǔ)容量為 64 b 至 6 Tb 不等，接口有 I2C、MMC、并行、eMMC、串行、單線、SPI、UFS、Xccela 總線和 1-線。

Key Features

? Multi I/O Support - Single I/O, Dual I/O and Quad I/O

? Support DTR (Double Transfer Rate) Mode

? 8/16/32/64 byte Wrap-Around Read Mode

1. FEATURES

GENERAL

? Supports Serial Peripheral Interface -- Mode 0 and Mode 3

? Single Power Supply Operation

- 1.65 to 2.0 volt for read, erase, and program operations

? 512Mb: 536,870,912 x 1 bit structure or 268,435,456 x 2 bits (two I/O mode) structure or 134,217,728 x 4 bits (four I/O mode) structure

? Protocol Support

- Single I/O, Dual I/O and Quad I/O

? Latch-up protected to 100mA from -1V to Vcc +1V

? Fast read for SPI mode

- Support fast clock frequency up to 166MHz

- Support Fast Read, 2READ, DREAD, 4READ, QREAD instructions

- Support DTR (Double Transfer Rate) Mode

- Configurable dummy cycle number for fast read operation

? Quad Peripheral Interface (QPI) available

? Equal Sectors with 4K byte each, or Equal Blocks with 32K byte each or Equal Blocks with 64K byte each

- Any Block can be erased individually

? Programming :

- 256byte page buffer

- Quad Input/Output page program(4PP) to enhance program performance

? Typical 100,000 erase/program cycles

? 20 years data retention

SOFTWARE FEATURES

? Input Data Format

- 1-byte Command code

? Advanced Security Features

- Block lock protection The BP0-BP3 and T/B status bits define the size of the area to be protected against program and erase instructions

- Advanced sector protection function

? Additional 8K bit security OTP

- Features unique identifier

- Factory locked identifiable, and customer lockable

? Command Reset

? Program/Erase Suspend and Resume operation

? Electronic Identification

- JEDEC 1-byte manufacturer ID and 2-byte device ID

- RES command for 1-byte Device ID

- REMS command for 1-byte manufacturer ID and 1-byte device ID

? Support Serial Flash Discoverable Parameters (SFDP) mode

HARDWARE FEATURES

? SCLK Input

- Serial clock input

? SI/SIO0

- Serial Data Input or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode

? SO/SIO1

- Serial Data Output or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode

? WP#/SIO2

- Hardware write protection or serial data Input/Output for 4 x I/O read mode

? RESET#

- Hardware Reset pin

? RESET#/SIO3 * or NC/SIO3 *

- Hardware Reset pin or Serial input & Output for 4 x I/O read mode or

- No Connection or Serial input & Output for 4 x I/O read mode

* Depends on part number options

? PACKAGE

- 16-pin SOP (300mil)

- 24-Ball BGA (5x5 ball array)

- 8-land WSON (8x6mm 3.4 x 4.3EP)

- All devices are RoHS Compliant and Halogen-free

2. GENERAL DESCRIPTION

MX25U51245G is 512Mb bits Serial NOR Flash memory, which is configured as 67,108,864 x 8 internally. When it is in two or four I/O mode, the structure becomes 268,435,456 bits x 2 or 134,217,728 bits x 4. MX25U51245G feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single I/O mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input.

When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# and RESET# pin become SIO0 pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output.

The MX25U51245G MXSMIO? (Serial Multi I/O) provides sequential read operation on whole chip.

After program/erase command is issued, auto program/erase algorithms which program/erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256 bytes) basis, or word basis for erase command is executed on sector (4K-byte), block (32K-byte), or block (64K-byte), or whole chip basis.

To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit.

Advanced security features enhance the protection and security functions, please see security features section for more details.

When the device is not in operation and CS# is high, it is put in standby mode.

The MX25U51245G utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles.