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首頁(yè)>MX25U51245GMI0A>規(guī)格書詳情

MX25U51245GMI0A中文資料????????????旺宏電子數(shù)據(jù)手冊(cè)PDF規(guī)格書

MX25U51245GMI0A
廠商型號(hào)

MX25U51245GMI0A

功能描述

1.8V, 512M-BIT [x 1/x 2/x 4] CMOS MXSMIO? (SERIAL MULTI I/O) FLASH MEMORY

文件大小

1.66812 Mbytes

頁(yè)面數(shù)量

127 頁(yè)

生產(chǎn)廠商

MCNIX

中文名稱

????????????旺宏電子

網(wǎng)址

網(wǎng)址

數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2025-8-15 20:00:00

人工找貨

MX25U51245GMI0A價(jià)格和庫(kù)存,歡迎聯(lián)系客服免費(fèi)人工找貨

MX25U51245GMI0A規(guī)格書詳情

Key Features

? Multi I/O Support - Single I/O, Dual I/O and Quad I/O

? Support DTR (Double Transfer Rate) Mode

? 8/16/32/64 byte Wrap-Around Read Mode

1. FEATURES

GENERAL

? Supports Serial Peripheral Interface -- Mode 0 and Mode 3

? Single Power Supply Operation

- 1.65 to 2.0 volt for read, erase, and program operations

? 512Mb: 536,870,912 x 1 bit structure or 268,435,456 x 2 bits (two I/O mode) structure or 134,217,728 x 4 bits (four I/O mode) structure

? Protocol Support

- Single I/O, Dual I/O and Quad I/O

? Latch-up protected to 100mA from -1V to Vcc +1V

? Fast read for SPI mode

- Support fast clock frequency up to 166MHz

- Support Fast Read, 2READ, DREAD, 4READ, QREAD instructions

- Support DTR (Double Transfer Rate) Mode

- Configurable dummy cycle number for fast read operation

? Quad Peripheral Interface (QPI) available

? Equal Sectors with 4K byte each, or Equal Blocks with 32K byte each or Equal Blocks with 64K byte each

- Any Block can be erased individually

? Programming :

- 256byte page buffer

- Quad Input/Output page program(4PP) to enhance program performance

? Typical 100,000 erase/program cycles

? 20 years data retention

SOFTWARE FEATURES

? Input Data Format

- 1-byte Command code

? Advanced Security Features

- Block lock protection The BP0-BP3 and T/B status bits define the size of the area to be protected against program and erase instructions

- Advanced sector protection function

? Additional 8K bit security OTP

- Features unique identifier

- Factory locked identifiable, and customer lockable

? Command Reset

? Program/Erase Suspend and Resume operation

? Electronic Identification

- JEDEC 1-byte manufacturer ID and 2-byte device ID

- RES command for 1-byte Device ID

- REMS command for 1-byte manufacturer ID and 1-byte device ID

? Support Serial Flash Discoverable Parameters (SFDP) mode

HARDWARE FEATURES

? SCLK Input

- Serial clock input

? SI/SIO0

- Serial Data Input or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode

? SO/SIO1

- Serial Data Output or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode

? WP#/SIO2

- Hardware write protection or serial data Input/Output for 4 x I/O read mode

? RESET#

- Hardware Reset pin

? RESET#/SIO3 * or NC/SIO3 *

- Hardware Reset pin or Serial input & Output for 4 x I/O read mode or

- No Connection or Serial input & Output for 4 x I/O read mode

* Depends on part number options

? PACKAGE

- 16-pin SOP (300mil)

- 24-Ball BGA (5x5 ball array)

- 8-land WSON (8x6mm 3.4 x 4.3EP)

- All devices are RoHS Compliant and Halogen-free

2. GENERAL DESCRIPTION

MX25U51245G is 512Mb bits Serial NOR Flash memory, which is configured as 67,108,864 x 8 internally. When it is in two or four I/O mode, the structure becomes 268,435,456 bits x 2 or 134,217,728 bits x 4. MX25U51245G feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single I/O mode. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input.

When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# and RESET# pin become SIO0 pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output.

The MX25U51245G MXSMIO? (Serial Multi I/O) provides sequential read operation on whole chip.

After program/erase command is issued, auto program/erase algorithms which program/erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page (256 bytes) basis, or word basis for erase command is executed on sector (4K-byte), block (32K-byte), or block (64K-byte), or whole chip basis.

To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit.

Advanced security features enhance the protection and security functions, please see security features section for more details.

When the device is not in operation and CS# is high, it is put in standby mode.

The MX25U51245G utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles.

供應(yīng)商 型號(hào) 品牌 批號(hào) 封裝 庫(kù)存 備注 價(jià)格
MX
24+
NA/
3319
原裝現(xiàn)貨,當(dāng)天可交貨,原型號(hào)開(kāi)票
詢價(jià)
MXIC
18+
N/A
4990
一級(jí)代理,專注軍工、汽車、醫(yī)療、工業(yè)、新能源、電力
詢價(jià)
MXIC
2024+
N/A
500000
誠(chéng)信服務(wù),絕對(duì)原裝原盤
詢價(jià)
MXIC
23+
BGA24
3000
一級(jí)代理原廠VIP渠道,專注軍工、汽車、醫(yī)療、工業(yè)、
詢價(jià)
Macronix
25+
25000
原廠原包 深圳現(xiàn)貨 主打品牌 假一賠百 可開(kāi)票!
詢價(jià)
原裝正品MXIC
23+
BGA
12800
公司只有原裝 歡迎來(lái)電咨詢。
詢價(jià)
Macronix
23+/24+
24-TBGA
8600
只供原裝進(jìn)口公司現(xiàn)貨+可訂貨
詢價(jià)
Macronix
25+
電聯(lián)咨詢
7800
公司現(xiàn)貨,提供拆樣技術(shù)支持
詢價(jià)
MACRONIX INTERNATIONAL
2022+
原廠原包裝
8600
全新原裝 支持表配單 中國(guó)著名電子元器件獨(dú)立分銷
詢價(jià)
Macronix
/ROHS.original
24-CSPBGA(6x8)
19344
﹤原裝元器件﹥現(xiàn)貨特價(jià)/供應(yīng)元器件代理經(jīng)銷。歡迎咨
詢價(jià)