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MT4LC4M4B1中文資料鎂光數(shù)據(jù)手冊PDF規(guī)格書

MT4LC4M4B1
廠商型號(hào)

MT4LC4M4B1

功能描述

DRAM

文件大小

360.23 Kbytes

頁面數(shù)量

20

生產(chǎn)廠商 Micron Technology
企業(yè)簡稱

MICRON鎂光

中文名稱

美國鎂光科技有限公司官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊

下載地址一下載地址二到原廠下載

更新時(shí)間

2025-8-2 22:50:00

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MT4LC4M4B1規(guī)格書詳情

GENERAL DESCRIPTION

The 4 Meg x 4 DRAM is a randomly accessed, solidstate memory containing 16,777,216 bits organized in a x4 configuration. RAS# is used to latch the row address (first 11 bits for 2K and first 12 bits for 4K). Once the page has been opened by RAS#, CAS# is used to latch the column address (the latter 11 bits for 2K and the latter 10 bits for 4K; address pins A10 and A11 are “Don’t Care”).

FEATURES

? Industry-standard x4 pinout, timing, functions, and packages

? High-performance, low-power CMOS silicon-gate process

? Single power supply (+3.3V ±0.3V or +5V ±0.5V)

? All inputs, outputs and clocks are TTL-compatible

? Refresh modes: RAS#-ONLY, HIDDEN and CAS#- BEFORE-RAS# (CBR)

? Optional self refresh (S) for low-power data retention

? 11 row, 11 column addresses (2K refresh) or 12 row, 10 column addresses (4K refresh)

? FAST-PAGE-MODE (FPM) access

? 5V tolerant inputs and I/Os on 3.3V devices

產(chǎn)品屬性

  • 型號(hào):

    MT4LC4M4B1

  • 制造商:

    MICRON

  • 制造商全稱:

    Micron Technology

  • 功能描述:

    DRAM

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