GENERAL DESCRIPTION

The 256Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456-bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 67,108,864-bit banks is organized as 4,096 rows by 512 columns by 32 bits.

FEATURES

? PC100 functionality

? Fully synchronous; all signals registered on positive edge of system clock

? Internal pipelined operation; column address can be changed every clock cycle

? Internal banks for hiding row access/precharge

? Programmable burst lengths: 1, 2, 4, 8, or full page

? Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes

? Self Refresh Mode

? 64ms, 4,096-cycle refresh (15.6μs/row)

? LVTTL-compatible inputs and outputs

? Single +3.3V ±0.3V power supply

? Supports CAS latency of 1, 2, and 3