特性 Features

? VDD = 1.8V ±0.1V, VDDQ = 1.8V ±0.1V

? JEDEC-standard 1.8V I/O (SSTL_18-compatible)

? Differential data strobe (DQS, DQS#) option

? 4n-bit prefetch architecture

? Duplicate output strobe (RDQS) option for x8

? DLL to align DQ and DQS transitions with CK

? 4 internal banks for concurrent operation

? Programmable CAS latency (CL)

? Posted CAS additive latency (AL)

? WRITE latency = READ latency - 1 t

CK

? Selectable burst lengths: 4 or 8

? Adjustable data-output drive strength

? 64ms, 8192-cycle refresh

? On-die termination (ODT)

? Industrial temperature (IT) option

? RoHS-compliant

? Supports JEDEC clock jitter specification

Options1

? Configuration

– 128 Meg x 4 (32 Meg x 4 x 4 banks)

– 64 Meg x 8 (16 Meg x 8 x 4 banks)

– 32 Meg x 16 (8 Meg x 16 x 4 banks)

? FBGA package (Pb-free) – x16

– 84-ball FBGA (8mm x 12.5mm) Rev. G

– 84-ball FBGA (8mm x 12.5mm) Rev. H

? FBGA package (Pb-free) – x4, x8

– 60-ball FBGA (8mm x 10mm) Rev. G

– 60-ball FBGA (8mm x 10mm) Rev. H

? FBGA package (lead solder) – x16

– 84-ball FBGA (8mm x 12.5mm) Rev. G

? FBGA package (lead solder) – x4, x8

– 60-ball FBGA (8mm x 10mm) Rev. G

? Timing – cycle time

– 1.875ns @ CL = 7 (DDR2-1066)

– 2.5ns @ CL = 5 (DDR2-800)

– 3.0ns @ CL = 5 (DDR2-667)

? Self refresh

– Standard None

– Low-power L

? Operating temperature

– Commercial (0°C ? TC ? +85°C)2

– Industrial (–40°C ? TC ? +95°C;

–40°C ? TA ? +85°C)

? Revision