Quad Digital Signal Processor

? Four StarCore? SC140 DSP extended cores, each with an SC140

DSP core, 224 Kbyte of internal SRAM M1 memory (1436 Kbyte

total), 16 way 16 Kbyte instruction cache (ICache), four-entry

write buffer, external cache support, programmable interrupt

controller (PIC), local interrupt controller (LIC), and low-power

Wait and Stop processing modes.

? 475 Kbyte M2 memory for critical data/temporary data buffering.

? 4 Kbyte boot ROM.

? M2-accessible multi-core MQBus connecting the M2 memory

with all four cores, operating at the core frequency, with data bus

access of up to 128-bit reads and up to 64-bit writes, central

efficient round-robin arbiter for core access to the bus, and atomic

control of M2 memory access by the cores and local bus.

? Internal PLL configured are reset by configuration signal values.

? 60x-compatible system bus with 64 or 32 bit data and 32-bit

address bus, support for multi-master designs, four-beat burst

transfers (eight-beat in 32-bit data mode), port size of 64/32/16/8

bits controlled by the internal memory controller,.access to

external memory or peripherals, access by an external host to

internal resources, slave support with direct access to internal

resources including M1 and M2 memories, and on-device

arbitration for up to four master devices. (Continue ...)