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MPC8533EVTARJA

PowerQUICC, 32 Bit Power Arch SoC, 1067MHz, DDR1/2, PCI/PCIe, 1GbE, USB, SEC, 0 to 90C, Rev 2.1; ? Embedded e500 core, initial offerings up to 667 MHz, targeting up to 1.0 GHz ? Dual dispatch superscalar, 7-stage pipeline design with out-of-order issue and execution\n? 2,240 MIPS at 1.0 GHz (estimated Dhrystone 2.1)\n? 36-bit physical addressing\n? Enhanced hardware and software debug support\n? Double-precision embedded scalar and vector floating-point APUs\n? Memory management unit (MMU)\n? Double-precision embedded scalar and vector floating-point APUs\n? Integrated L1/L2 cache ? L1 cache—32 KB data and 32 KB instruction cache with line-locking support\n? L2 cache—256 KB (8-way set associative); 256/128/64/32 KB can be used as SRAM\n? L1 and L2 hardware coherency\n? L2 cache and I/O transactions can be stashed into L2 cache regions\n? Integrated DDR memory controller with full ECC support, offering: ? 200 MHz clock rate (400 MHz data rate), 64-bit, 2.5V/2.6V I/O, DDR SDRAM\n? 267 MHz clock rate (up to 533 MHz data rate), 64-bit, 1.8V I/O, DDR2 SDRAM\n? Integrated security engine supporting DES, 3DES, MD-5, SHA-1/2, AES, RSA, RNG, Kasumi F8/F9 and ARC-4 encryption algorithms\n? Two on-chip Three Speed Ethernet controllers (ETSECs) supporting 10 Mbps, 100 Mbps and 1 Gbps Ethernet/IEEE? 802.3 networks with MII, RMII, RGMII, and RTBI physical interfaces: ? TCP/UDP/IP checksum acceleration\n? Advanced QoS features\n? General-purpose input/output (GPIO)\n? PCI Express high-speed interconnect interfaces, supporting combinations of dual x4 and single x1 PCI Express\n? On-chip network (OCeaN) switch fabric\n? PCI interface support ? 32-bit PCI 2.2 bus controller (up to 66MHz, 3.3V I/O)\n? Local bus ? ?166 MHz, 32-bit, 3.3V I/O, local bus with memory controller\n? Integrated four-channel DMA controller ? ?Multiplexed 32-bit address and data operating up to 133 MHz\n? ?32-, 16- and 8-bit port sizes controlled by on-chip memory controller\n? Dual I2C and DUART support\n? Dual I2C interfaces (master or slave mode)\n? Programmable interrupt controller (PIC)\n? IEEE 1149.1 JTAG test access port\n? 1.0V core voltage with 3.3V and 2.5V I/O\n? 783-pin FC-BGA package\n;

The MPC8533E PowerQUICC? III communications processor offers high level of integration and performance for Ethernet-only or PCIe interworking applications, such as enterprise networking and advanced multi-function printer (MFP) and imaging applications.\nIncludes enhanced peripherals, an integrated security engine, and a wide range of high-speed connectivity options\nSupports complex, computationally demanding control plane processing tasks\nComes optimized for power sensitive applications\nProvides a flexible SoC platform to accelerate time-to-market\nSimplifies board design\nAccess to the errata document for this device requires an NDA. Contact your local NXP? Sales Office or NXP Authorized Distributor.\n

MPC8533EVTARJB

PowerQUICC??III Integrated Processor Hardware Specifications

MPC8533EVTARXB

PowerQUICC??IIIIntegratedProcessorHardwareSpecifications

MPC8533HXAAFB

PowerQUICC??IIIIntegratedProcessorHardwareSpecifications

MPC8533HXAAGB

PowerQUICC??IIIIntegratedProcessorHardwareSpecifications

MPC8533HXAAJB

PowerQUICC??IIIIntegratedProcessorHardwareSpecifications

MPC8533HXAAXB

PowerQUICC??IIIIntegratedProcessorHardwareSpecifications

MPC8533HXALFB

PowerQUICC??IIIIntegratedProcessorHardwareSpecifications

MPC8533HXALGB

PowerQUICC??IIIIntegratedProcessorHardwareSpecifications

MPC8533HXALJB

PowerQUICC??IIIIntegratedProcessorHardwareSpecifications