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首頁(yè)>MPC2104P>規(guī)格書詳情

MPC2104P中文資料摩托羅拉數(shù)據(jù)手冊(cè)PDF規(guī)格書

MPC2104P
廠商型號(hào)

MPC2104P

功能描述

256KB/512KB BurstRAM Secondary Cache Modules for PowerPC PReP/CHRP Platforms

文件大小

158.43 Kbytes

頁(yè)面數(shù)量

16 頁(yè)

生產(chǎn)廠商 Motorola, Inc
企業(yè)簡(jiǎn)稱

MOTOROLA摩托羅拉

中文名稱

加爾文制造公司官網(wǎng)

原廠標(biāo)識(shí)
數(shù)據(jù)手冊(cè)

下載地址一下載地址二到原廠下載

更新時(shí)間

2025-7-26 23:00:00

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MPC2104P規(guī)格書詳情

The MPC2104P (256KB) and MPC2105P (512KB) are designed to provide burstable, high performance L2 cache for the PowerPC 60x microprocessor family in conformance with the PowerPC Reference Platform (PReP) and the PowerPC Common Hardware Reference Platform (CHRP) specifications.

All of these cache modules are plug and pin compatible with each other.

? PowerPC–Style Burst Counter On Chip

? Pipeline Data I/O

? Plug and Pin Compatibility

? Multiple Clock Pins for Reduced Loading

? All Cache Data and Tag I/Os are LVTTL (3.3 V) Compatible

? Three State Outputs

? Buffered Addresses to Data RAMs for Reduced Loading

? Fast Module Clock Rates: Up to 66 MHz

? Fast SRAM Access Times: 9 ns for Tag RAM Match 8 ns for Data RAM

? Decoupling Capacitors for Each Fast Static RAM

? High Quality Multi–Layer FR4 PWB With Separate Power and Ground Planes

? 178 Pin Card Edge Module

? Burndy Connector, Part Number: ELF178KSC–3Z50

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3860
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NA
610
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50
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N/A
23+
SMD
3500
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2000
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