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MK2049-01

Communications Clock PLL

Description TheMK2049isaPhase-LockedLoop(PLL)basedclocksynthesizer,whichacceptsan8kHzclockinputasareferenceandgeneratesT1,E1,T3,E3,andOC3frequencies.ThedevicecanalsoacceptaT1,E1,T3,orE3inputclockandprovidethesameoutputforlooptiming.Alloutputsare

MK2049-01S

Communications Clock PLL

Description TheMK2049isaPhase-LockedLoop(PLL)basedclocksynthesizer,whichacceptsan8kHzclockinputasareferenceandgeneratesT1,E1,T3,E3,andOC3frequencies.ThedevicecanalsoacceptaT1,E1,T3,orE3inputclockandprovidethesameoutputforlooptiming.Alloutputsare

MK2049-01SI

Communications Clock PLL

Description TheMK2049isaPhase-LockedLoop(PLL)basedclocksynthesizer,whichacceptsan8kHzclockinputasareferenceandgeneratesT1,E1,T3,E3,andOC3frequencies.ThedevicecanalsoacceptaT1,E1,T3,orE3inputclockandprovidethesameoutputforlooptiming.Alloutputsare

MK2049-01SITR

Communications Clock PLL

Description TheMK2049isaPhase-LockedLoop(PLL)basedclocksynthesizer,whichacceptsan8kHzclockinputasareferenceandgeneratesT1,E1,T3,E3,andOC3frequencies.ThedevicecanalsoacceptaT1,E1,T3,orE3inputclockandprovidethesameoutputforlooptiming.Alloutputsare

MK2049-01STR

Communications Clock PLL

Description TheMK2049isaPhase-LockedLoop(PLL)basedclocksynthesizer,whichacceptsan8kHzclockinputasareferenceandgeneratesT1,E1,T3,E3,andOC3frequencies.ThedevicecanalsoacceptaT1,E1,T3,orE3inputclockandprovidethesameoutputforlooptiming.Alloutputsare

MK2049-01S

Communications Clock PLL;