描述 Description

The MC74VHC240 is an advanced high speed CMOS octal bus buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The MC74VHC240 is an inverting 3-state buffer, and has two active-low output enables. This device is designed to drive bus lines or buffer memory address registers. The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output. The inputs tolerate voltages up to 7V, allowing the interface of 5V systems to 3V systems.

特性 Features

? High Speed: tPD = 3.6ns (Typ) at VCC = 5V
? Low Power Dissipation: ICC = 4μA (Max) at TA = 25 C
? High Noise Immunity: VNIH = VNIL = 28% VCC
? Power Down Protection Provided on Inputs
? Balanced Propagation Delays
? Designed for 2V to 5.5V Operating Range
? Low Noise: VOLP = 0.9V (Max)
? Pin and Function Compatible with Other Standard Logic Families
? Latchup Performance Exceeds 300mA
? ESD Performance: HBM > 2000V; Machine Model > 200V
? Chip Complexity: 120 FETs or 30 Equivalent Gates
? These devices are available in Pb-free package(s). Specifications herein apply to both standard and Pb-free devices. Please see our website at www.onsemi.com for specific Pb-free orderable part numbers, or contact your local ON Semiconductor sales office or representative.

簡介

MC74VHC240屬于集成電路（IC）的緩沖器驅動器接收器收發(fā)器。由制造生產的MC74VHC240緩沖器，驅動器，接收器，收發(fā)器邏輯緩沖器、驅動器、接收器和收發(fā)器允許隔離對某個電路的邏輯信號的訪問，以用于另一電路。緩沖器將其輸入信號（不變或反相）傳遞到其輸出，并可能用于清除弱信號或驅動負載。在布爾邏輯仿真器中，緩沖器主要用于增加傳播延遲。邏輯接收器和收發(fā)器允許在數據總線之間進行隔離通信。