The MC14508B dual 4–bit latch is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. The part consists of two identical, independent 4–bit latches with separate Strobe (ST) and Master Reset (MR) controls. Separate Disable inputs force the outputs to a high impedance state and allow the devices to be used in time sharing bus line applications.

These complementary MOS latches find primary use in buffer storage, holding register, or general digital logic functions where low power dissipation and/or high noise immunity is desired.

? 3–State Output

? Supply Voltage Range = 3.0 Vdc to 18 Vdc

? Capable–of Driving Two Low–power TTL Loads or One Low–power Schottky TTL Load over the Rated Temperature Range