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MC14094B

8-Stage Shift/Store Register with Three-State Outputs

TheMC14094Bcombinesan8?stageshiftregisterwithadatalatchforeachstageanda3?stateoutputfromeachlatch.Dataisshiftedonthepositiveclocktransitionandisshiftedfromtheseventhstagetotwoserialoutputs.TheQSoutputdataisforuseinhigh?speedcascadedsystems.TheQSou

MC14094B

8-Stage Shift/Store Register with Three-State Outputs

TheMC14094Bcombinesan8?stageshiftregisterwithadatalatchforeachstageanda3?stateoutputfromeachlatch.Dataisshiftedonthepositiveclocktransitionandisshiftedfromtheseventhstagetotwoserialoutputs.TheQSoutputdataisforuseinhigh?speedcascadedsystems.TheQSou

MC14094B

8-Stage Shift/Store Register with Three-State Outputs;

TheMC14094B combines an 8–stage shift register with adata latch for each stage and a three–state output from each latch. Datais shifted on the positive clock transition and is shifted from the seventh stage to two serial outputs. The QSoutput data is forusein high–speed cascaded systems. The Q′Soutput data is shifted on the following negative clock transition for use in low–speed cascaded systems. Datafrom each stage of the shift register is latched on the negative transitionof the strobe input. Data propagates through the latch while strobe is high. Outputsof the eightdata latches are controlled by three–state buffers whichare placed inthe high–impedance state by a logic Low on Output Enable.? Three–State Outputs\n? Capable of Driving Two Low–Power TTL Loads or One Low–Power Schottky TTL Load Over the Rated Temperature Range\n? Input Diode Protection\n? Data Latch\n? Dual Outputs for Data Out on Both Positive and Negative Clock Transitions\n? Useful for Serial–to–Parallel Data Conversion\n? Pin–for–Pin Compatible with CD4094B\n

MC14094B

8 位存儲/移位寄存器，帶三態(tài)輸出; ? Three-State Outputs\n? Capable of Driving Two Low-Power TTL Loads or One Low-Power Schottky TTL Load Over the Rated Temperature Range\n? Input Diode Protection\n? Data Latch\n? Dual Outputs for Data Out on Both Positive and Negative Clock Transitions\n? Useful for Serial-to-Parallel Data Conversion\n? Pin-for-Pin Compatible with CD4094B\n? Pb-Free Packages are Available*\n;

The MC14094B combines an 8-stage shift register with a data latch for each stage and a three-state output from each latch. Data is shifted on the positive clock transition and is shifted from the seventh stage to two serial outputs. The QS output data is for use in high-speed cascaded systems. The Q S output data is shifted on the following negative clock transition for use in low-speed cascaded systems. Data from each stage of the shift register is latched on the negative transition of the strobe input. Data propagates through the latch while strobe is high. Outputs of the eight data latches are controlled by three-state buffers which are placed in the high-impedance state by a logic Low on Output Enable.

MC14094B

8??tage Shift/Store Register with Three??tate Outputs

MC14094B

8-Stage Shift/Store Register with Three-State Outputs

MC14094BCP

8-Stage Shift/Store Register with Three-State Outputs

TheMC14094Bcombinesan8?stageshiftregisterwithadatalatchforeachstageanda3?stateoutputfromeachlatch.Dataisshiftedonthepositiveclocktransitionandisshiftedfromtheseventhstagetotwoserialoutputs.TheQSoutputdataisforuseinhigh?speedcascadedsystems.TheQSou

MC14094BCPG

8-Stage Shift/Store Register with Three-State Outputs

TheMC14094Bcombinesan8?stageshiftregisterwithadatalatchforeachstageanda3?stateoutputfromeachlatch.Dataisshiftedonthepositiveclocktransitionandisshiftedfromtheseventhstagetotwoserialoutputs.TheQSoutputdataisforuseinhigh?speedcascadedsystems.TheQSou

MC14094BD

8-Stage Shift/Store Register with Three-State Outputs

TheMC14094Bcombinesan8?stageshiftregisterwithadatalatchforeachstageanda3?stateoutputfromeachlatch.Dataisshiftedonthepositiveclocktransitionandisshiftedfromtheseventhstagetotwoserialoutputs.TheQSoutputdataisforuseinhigh?speedcascadedsystems.TheQSou

MC14094BDG

8-Stage Shift/Store Register with Three-State Outputs

TheMC14094Bcombinesan8?stageshiftregisterwithadatalatchforeachstageanda3?stateoutputfromeachlatch.Dataisshiftedonthepositiveclocktransitionandisshiftedfromtheseventhstagetotwoserialoutputs.TheQSoutputdataisforuseinhigh?speedcascadedsystems.TheQSou