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MC14042

Quad Transparent Latch

TheMC14042BQuadTransparentLatchisconstructedwithMOSP?channelandN?channelenhancementmodedevicesinasinglemonolithicstructure.Eachlatchhasaseparatedatainput,butallfourlatchesshareacommonclock.Theclockpolarity(highorlow)usedtostrobedatathroughthelatchesc

MC14042

Quad Transparent Latch;

MC14042B

Quad transparent latch;

The MC14042B Quad Transparent Latch is constructed with MOS P–channel and N–channel enhancement mode devices in a single monolithic structure. Each latch has a separate data input, but all four latches share a common clock. The clock polarity (high or low) used to strobe data through the latches can be reversed using the polarity input. Information present at the data input is transferred to outputs Q and Q during the clock level which is determined by the polarity input. When the polarity input is in the logic “0” state, data is transferred during the low clock level, and when the polarity input is in the logic “1” state the transfer occurs during the high clock level.? Buffered Data Inputs\n? Common Clock\n? Clock Polarity Control\n? Q and Q Outputs\n? Double Diode Input Protection\n? Supply Voltage Range = 3.0 Vdc to 1 8 Vdc\n? Capable of Driving Two Low–power TTL Loads or One Low–power\nSchottky TTL Load Over the Rated Temperature Range

MC14042B

四路透明鎖存; ? Buffered Data Inputs\n? Common Clock\n? Clock Polarity Control\n? Q and Qbar Outputs\n? Double Diode Input Protection\n? Supply Voltage Range = 3.0 Vdc to 1 8 Vdc\n? Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range\n? Pb-Free Packages are Available*\n;

The MC14042B Quad Transparent Latch is constructed with MOS P-channel and N-channel enhancement mode devices in a single monolithic structure. Each latch has a separate data input, but all four latches share a common clock. The clock polarity (high or low) used to strobe data through the latches can be reversed using the polarity input. Information present at the data input is transferred to outputs Q and Q during the clock level which is determined by the polarity input. When the polarity input is in the logic \"0\" state, data is transferred during the low clock level, and when the polarity input is in the logic \"1\" state the transfer occurs during the high clock level.

MC14042B

Quad Transparent Latch

TheMC14042BQuadTransparentLatchisconstructedwithMOSP?channelandN?channelenhancementmodedevicesinasinglemonolithicstructure.Eachlatchhasaseparatedatainput,butallfourlatchesshareacommonclock.Theclockpolarity(highorlow)usedtostrobedatathroughthelatchesc

MC14042B

QUAD TRANSPARENT LATCH

TheMC14042BQuadTransparentLatchisconstructedwithMOSP–channelandN–channelenhancementmodedevicesinasinglemonolithicstructure.Eachlatchhasaseparatedatainput,butallfourlatchesshareacommonclock.Theclockpolarity(highorlow)usedtostrobedatathroughthelatchesc

MC14042B

CMOS LSI (LOW-POWER COMPLEMENTARY MOS) 3 1/2 DIGIT A/D CONVERTER

CMOSLSI(LOW-POWERCOMPLEMENTARYMOS)31/2DIGITA/DCONVERTER

MC14042BCL

QUAD TRANSPARENT LATCH

TheMC14042BQuadTransparentLatchisconstructedwithMOSP–channelandN–channelenhancementmodedevicesinasinglemonolithicstructure.Eachlatchhasaseparatedatainput,butallfourlatchesshareacommonclock.Theclockpolarity(highorlow)usedtostrobedatathroughthelatchesc

MC14042BCP

Quad Transparent Latch

TheMC14042BQuadTransparentLatchisconstructedwithMOSP?channelandN?channelenhancementmodedevicesinasinglemonolithicstructure.Eachlatchhasaseparatedatainput,butallfourlatchesshareacommonclock.Theclockpolarity(highorlow)usedtostrobedatathroughthelatchesc

MC14042BCP

QUAD TRANSPARENT LATCH

TheMC14042BQuadTransparentLatchisconstructedwithMOSP–channelandN–channelenhancementmodedevicesinasinglemonolithicstructure.Eachlatchhasaseparatedatainput,butallfourlatchesshareacommonclock.Theclockpolarity(highorlow)usedtostrobedatathroughthelatchesc