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MC10EL15

1:4 Clock Distribution Chip

TheMC10EL/100EL15isalowskew1:4clockdistributionchipdesignedexplicitlyforlowskewclockdistributionapplications.TheVBBpin,aninternallygeneratedvoltagesupply,isavailabletothisdeviceonly.Forsingle-endedinputconditions,theunuseddifferentialinputisconnectedtoVBB

MC10EL15

Clock Distribution Chip, 1:4, ECL, 5.0 V; ? 50ps Output-to-Output Skew\n? Synchronous Enable/Disable\n? Multiplexed Clock Input\n? ESD Protection: > 1 KV HBM, > 100 V MM\n? PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V\n? NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V\n? Internal Input Pulldown Resistors on CLKs, SCLK, SEL, and ENbar.\n? Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test\n? Moisture Sensitivity Level 1For Additional Information, see Application Note AND8003/D\n? Flammability Rating: UL-94 code V-0 @ 1/8\", Oxygen Index 28 to 34\n? Transistor Count = 103 devices\n? Pb-Free Packages are Available\n;

The MC10EL/100EL15 is a low skew 1:4 clock distribution chip designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. If a single-ended input is to be used the VBB output should be connected to the CLK input and bypassed to ground via a 0.01 F capacitor. The VBB output is designed to act as the switching reference for the input of the EL15 under single-ended input conditions, as a result this pin can only source/sink up to 0.5mA of current. The EL15 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pulldown resistor) the SEL pin will select the differential clock input. The common enable (ENbar) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input.The 100 series contains temperature compensation.

MC10EL15

5V ECL 1:4 Clock Distribution Chip

MC10EL15

5V ECL 1:4 Clock Distribution Chip

MC10EL15_05

5V ECL 1:4 Clock Distribution Chip

MC10EL15_16

5V ECL 1:4 Clock Distribution Chip

MC10EL15D

5V ECL 1:4 Clock Distribution Chip

MC10EL15DG

5V ECL 1:4 Clock Distribution Chip

MC10EL15DG

5V ECL 1:4 Clock Distribution Chip

MC10EL15DR2

5V ECL 1:4 Clock Distribution Chip