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MC10E451

6-BIT D REGISTER DIFFERENTIAL DATA AND CLOCK

Description TheMC10E/100E451containssixD?typeflip?flopswithsingle?endedoutputsanddifferentialdatainputs.Thecommonclockinputisalsodifferential.Theregistersaretriggeredbyapositivetransitionofthepositiveclock(CLK)input. Features ?DifferentialInputs:Dataand

MC10E451

MC10E451: 5.0 V ECL 6-Bit D Register Differential Data and Clock; Differential Inputs: Data and Clock\nVBB Output\n1100MHz Min. Toggle Frequency\nAsynchronous Master Reset\nPECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V\nNECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V\nInternal Input Pulldown Resistors\nESD Protection: > 2 kV HBM, > 200 V MM\nMeets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test\nMoisture Sensitivity Level 1For Additional Information, see Application Note AND8003/D\nFlammability Rating: UL-94 code V-0 @ 1/8\", Oxygen Index 28 to 34\nTransistor Count = 348 devices\nPb-Free Packages are Available\n;

The MC10E/100E451 contains six D-type flip-flops with single-ended outputs and differential data inputs. The common clock input is also differential. The registers are triggered by a positive transition of the positive clock (CLK) input.A HIGH on the Master Reset (MR) input resets all Q outputs to LOW.The differential input structures are clamped so that the inputs of unused registers can be left open without upsetting the bias network of the device. The clamping action will assert the Dbar and the CLKbar sides of the inputs. Because of the edge triggered flip-flop nature of the device simultaneously opening both the clock and data inputs will result in an output which reaches an unidentified but valid state. Note that the input clamps only operate when both inputs fall to 2.5 V below VCC.The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.The 100 Series contains temperature compensation.

MC10E451

5V ECL 6??it D Register Differential Data and Clock

MC10E451

5 V ECL 6-Bit D Register Differential Data and Clock

MC10E451FN

6-BIT D REGISTER DIFFERENTIAL DATA AND CLOCK

Description TheMC10E/100E451containssixD?typeflip?flopswithsingle?endedoutputsanddifferentialdatainputs.Thecommonclockinputisalsodifferential.Theregistersaretriggeredbyapositivetransitionofthepositiveclock(CLK)input. Features ?DifferentialInputs:Dataand

MC10E451_06

5V ECL 6??it D Register Differential Data and Clock

MC10E451_16

5 V ECL 6-Bit D Register Differential Data and Clock

MC10E451FN

5V ECL 6??it D Register Differential Data and Clock

MC10E451FNG

5V ECL 6??it D Register Differential Data and Clock

MC10E451FNG

5 V ECL 6-Bit D Register Differential Data and Clock