The MC10E/100E256 contains three 4:1 multiplexers followed by transparent latches with differential outputs. Separate Select controls are provided for the leading 2:1 mux pairs (see logic symbol).

When the Latch Enable (LEN) is LOW, the latch is transparent, and output data is controlled by the multiplexer select controls. A logic HIGH on LEN latches the outputs. The Master Reset (MR) overrides all other controls to set the Q outputs LOW.

The 100 Series contains temperature compensation

? 950 ps Max. D to Output

? 850 ps Max. LEN to Output

? Split Select

? Differential Outputs

? PECL Mode Operating Range: VCC= 4.2 V to 5.7 V with VEE= 0 V

? NECL Mode Operating Range: VCC= 0 V with VEE= –4.2 V to –5.7 V

? Internal Input Pulldown Resistors

? ESD Protection: > 1 KV HBM, > 75 V MM

? Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test

? Moisture Sensitivity Level 1 For Additional Information, see Application Note AND8003/D

? Flammability Rating: UL–94 code V–0 @ 1/8”, Oxygen Index 28 to 34

? Transistor Count = 280 devices