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MC100EL39

?2/4,?4/6 Clock Generation Chip

TheMC100LVEL39isalowskew÷2/4,÷4/6clockgenerationchipdesignedexplicitlyforlowskewclockgenerationapplications.TheMC100EL39ispinandfunctionallyequivalenttotheMC100LVEL39butisspecifiedforoperationatthestandard100KECLvoltagesupply. ?50psOutput-to-OutputS

MC100EL39

5V ECL ?2/4, ?4/6 Clock Generation Chip

TheMC100EL39isalowskew÷2/4,÷4/6clockgenerationchipdesignedexplicitlyforlowskewclockgenerationapplications.Theinternaldividersaresynchronoustoeachother,therefore,thecommonoutputedgesareallpreciselyaligned. Features ?50psOutput-to-OutputSkew ?Synchrono

MC100EL39

MC100EL39: 5.0 V ECL ÷2, ÷4, ÷8 Clock Generation Chip; 50 ps Output-to-Output Skew\nSynchronous Enable/Disable\nMaster Reset for Synchronization\nESD Protection: > 2 KV HBM, > 100 V MM\nThe 100 Series Contains Temperature Compensation\nPECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V\nNECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V\nInternal Input Pulldown Resistors on ENbar, MR, CLK(s), and DIVSEL(s)\nQ Output will Default LOW with Inputs Open or at VEE\nMeets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test\nFlammability Rating: UL-94 code V-0 @ 1/8\", Oxygen Index 28 to 34\nTransistor Count = 419 devices\nPb-Free Packages are Available\n;

The MC100EL39 is a low skew divide by 2/4, divide by 4/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned.The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differentia input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.The common enable (ENbar) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input.Upon startup, the internal flip-flops will attain a random state; therefore, for systems which utilize multiple EL39s, the master reset (MR) inputmust be asserted to ensure synchronization. For systems which only use one EL39, the MR pin need not be exercised as the internal divider design ensures synchronization between the divide by 2/4 and the divide by 4/6 outputs of a singledevice.

MC100EL39DW

?2/4,?4/6 Clock Generation Chip

TheMC100LVEL39isalowskew÷2/4,÷4/6clockgenerationchipdesignedexplicitlyforlowskewclockgenerationapplications.TheMC100EL39ispinandfunctionallyequivalenttotheMC100LVEL39butisspecifiedforoperationatthestandard100KECLvoltagesupply. ?50psOutput-to-OutputS

MC100EL39DW

5V ECL ?2/4, ?4/6 Clock Generation Chip

TheMC100EL39isalowskew÷2/4,÷4/6clockgenerationchipdesignedexplicitlyforlowskewclockgenerationapplications.Theinternaldividersaresynchronoustoeachother,therefore,thecommonoutputedgesareallpreciselyaligned. Features ?50psOutput-to-OutputSkew ?Synchrono

MC100EL39DWG

5V ECL ?2/4, ?4/6 Clock Generation Chip

TheMC100EL39isalowskew÷2/4,÷4/6clockgenerationchipdesignedexplicitlyforlowskewclockgenerationapplications.Theinternaldividersaresynchronoustoeachother,therefore,thecommonoutputedgesareallpreciselyaligned. Features ?50psOutput-to-OutputSkew ?Synchrono

MC100EL39DWR2

5V ECL ?2/4, ?4/6 Clock Generation Chip

TheMC100EL39isalowskew÷2/4,÷4/6clockgenerationchipdesignedexplicitlyforlowskewclockgenerationapplications.Theinternaldividersaresynchronoustoeachother,therefore,thecommonoutputedgesareallpreciselyaligned. Features ?50psOutput-to-OutputSkew ?Synchrono

MC100EL39DWR2G

5V ECL ?2/4, ?4/6 Clock Generation Chip

TheMC100EL39isalowskew÷2/4,÷4/6clockgenerationchipdesignedexplicitlyforlowskewclockgenerationapplications.Theinternaldividersaresynchronoustoeachother,therefore,thecommonoutputedgesareallpreciselyaligned. Features ?50psOutput-to-OutputSkew ?Synchrono

MC100EL39_16

5 V ECL Clock Generation Chip

MC100EL39DWR2G

5 V ECL Clock Generation Chip